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  1. Re: Actel Desktop Schematic Viewer
  2. Re: Nios Quartus II Question...
  3. Quartus II 2.2 smart compile ignoring .mif
  4. Re: Nios Quartus II Question...
  5. Xilinx
  6. FPGA congress on Asia
  7. Xilinx ISE 6.1i DCM is dead
  8. USB Transreceiver (PDIUSBP11A)
  9. How to use systemc together with VHDL or Verilog?
  10. platform flash as storage?
  11. Making hard macros in Xilinx FPGA Editor
  12. Xilinx source dragonsources
  13. Digilent board
  14. Reporting in ISE5.1 timing analyzer
  15. MICROBLAZE: Using external instruction memory
  16. ByteblasterMV and QuartusII 3.0
  17. back-annotate pin location with xilinx webpack 5.2
  18. IBUF, IBUFG, OBUF
  19. Xilinx ISE 6.1i
  20. 'RSVD' pin on V2/V2P
  21. spartan3 pin tables
  22. fpga +cpu + wireless
  23. Quartus internal synthesis more verbose?
  24. USB transceiver for FPGA
  25. Xilinx Timing Constraints for Asynchronous Logic (asynch latches)
  26. Spartan-3 : preconfiguration pull-up/float ?
  27. About two open source 32bit MCU
  28. What CPU for Quartus II?
  29. fft size in fpga
  30. logic from jed file
  31. Looking for Atmel dataflash VHDL model
  32. Spartan 3 ICAP primitive
  33. DDC design
  34. WebPack - mixed design flow
  35. Reconfiguration standards
  36. ATLV256 for Spartan 2
  37. need help with Xilinx ISE 4.2i software
  38. Z-busses and synthesis
  39. Downloading into XCV600 FPGA using PCI
  40. Foundation 3.1 to ISE 5.2
  41. Transistor count
  42. What are Pull ups?
  43. Newbie
  44. Error when downloading with EDK
  45. DCM not locking in XC2V4000
  46. TEST
  47. FPGA Reconfiguration Question
  48. Xilinx 6.1i on Red Hat 9
  49. Paging Peter Alfke (3S1000 pricing)
  50. Re: The real history of computer architecture: the short form
  51. Altera's Quartus II "smart compilation" feature killed my design?
  52. Xilinx-gdb Sources publicly available?
  53. Reading and processing input from graphics cards (DVI)?
  54. Time Killing Post P&R Simulation
  55. implementation error
  56. Webpack Vs. ISE
  57. xilinx ace ibis
  58. test signals for testing of leaf level entities in a design
  59. Newbee question? Schematic entry
  60. Duty cycle constraints and internal pulse shaping
  61. What clock domain is a Xilinx DCM LOCK signal in?
  62. Online Troubleshooters
  63. Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL license
  64. LVDS in cyclone
  65. LVDS
  66. ABEL help needed
  67. DDR in EDK 3.2sp2...
  68. Embedded/Microcontroller FPGA and Software Defined Radio
  69. simulating memory models in sopc builder
  70. Power on problems
  71. Crystal Input to FPGA
  72. Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
  73. cpld's in a DIL package available
  74. Power-on slope :Spartan IIE
  75. Xilinx clk to out variation
  76. ERROR:Pack:679 - Unable to obey design constraints ....can anyone help
  77. EMAC in EDK...
  78. pipelined divider
  79. AWGN in VHDL
  80. Virtex II Pro Linux
  81. frequency constraint changes routability
  82. Programming Xilinx CPLD under linux
  83. Targetting RC1000 with Mediabench JPEG Application
  84. microblaze on XSV800
  85. Clock Synchronization of PC and FPGA
  86. Xilinx Platform Configuration, really cool devices (and avaialble!)
  87. Xilinx S3 I/O robustness question
  88. FPGA: Interfacing external NVRAM
  89. IP-Core CAN-Controller
  90. Impact error
  91. mouse to Nios Development kit
  92. FPGA start?
  93. system simulation and verification methods (NIOS)
  94. PIC Programming Help
  95. Re: Schematic simulation and then FPGA programming?
  96. Spartan3 multiplier
  97. Spartan 2 xc2s150
  98. CMOS camera w/ USB2 -- crazy?
  99. Stratix pricing
  100. VGA display
  101. Cpu Generator rel.1.00 released
  102. switching problem
  103. Re: Schematic simulation and then FPGA programming?
  104. Original (5V) Xilinx Spartan ?
  105. Automatic signal fanout management in an FPGA (Xilinx type in this case)
  106. Low-cost FPGA Development Board with built-in Computer core
  107. Schematic simulation and then FPGA programming?
  108. 200MHz ucf constraints for Xilinx DA Decimation by 2
  109. Filter Output Quantization in Digital Down Converter
  110. Q: Xilinx PROM file generation
  111. Writing a Xilnx testbench
  112. Include design file using QuartusII
  113. Sending and receiving Ethernet traffic
  114. ISE: use verilog-modules in an vhdl-design-flow
  115. Re: Flex6K configuration PROM
  116. Suitable FPGA architecture for Robots..
  117. SEK1054BOA LCD Technical datasheet
  118. Disable Pull up
  119. Flex6K configuration PROM
  120. How to contact the writer of Xilinx FPGA application notes?
  121. question about configue apex20k with ppa scheme
  122. More about metastability
  123. Memory
  124. More EDK Problems..... :-(
  125. Clock Recovery from 8B10B encoded Data Stream
  126. How to extend a pulse width without clock in CPLD!
  127. New to FPGA, seeking advice
  128. ISE 5.2 constraint file problem
  129. MICROBLAZE: user core problem
  130. Using a different editor for ISE 5
  131. Newbie CAN Core question - Student
  132. How to extend a pulse width without clock!
  133. OT: Block diagramming tools?
  134. Generating Asynchronous FIFO in Block Memory of Sparatn-II in CoreGen
  135. Re: Input comparator
  136. Test, please ignore
  137. Re: Xilinx Foundation Series 2.1i on Linux
  138. altera latch synthesis
  139. Re: A student's question
  140. Re: Input comparator
  141. EDK problem!
  142. Re: Complex digital ICs visual simulation?
  143. Re: Xilinx Foundation Series 2.1i on Linux
  144. Matlab: What do I need for modeling?
  145. Altera Devices
  146. Partial Reconfiguration : 2 reconfig modules
  147. DDR capabilities of a Virtex II device
  148. parallel port
  149. Virtex-E Select-RAM refresh rate
  150. Are there any free version uCOSII for Nios?
  151. BlockRam @ 333MHz
  152. Complex digital ICs visual simulation?
  153. Re: serie
  154. Re: A student's question
  155. Different types of ASICs?
  156. What does + synthesize to?
  157. Compact FIR filters with multiplier blocks?
  158. Re: How to use Modelsim-Altera to do the timing simulation?
  159. Re: Question conserning Altera's Quartus II
  160. A WEB site digesting FPGA boards and PC connectivity solutions?
  161. using CLKDLL, want: myclock <= CLKDV and LOCKED
  162. Parallel Cable III Problems
  163. Re: V2Pro, ML300 Linux reference design
  164. Shift register
  165. DSP
  166. how to design this datapath unit for DSP using VHDL/Verilog?
  167. Re: DCM divide/phase problem
  168. Mitigating metastability.
  169. Re: pricing, cyclone or spartan
  170. keep_hierarchy in project manager
  171. Configuration vhdl
  172. Xilinx Foundation Series F2.1i + win2k
  173. HDL Designer from Mentor
  174. Selecting between two clock signals
  175. Moving Sum
  176. Re: pricing, cyclone or spartan
  177. Period constraint
  178. Re: Lithium cell on Virtex2 Pro
  179. We are debugging a pci board and met some difficulties.
  180. Is Platform Flash PROM an electrically erasable??
  181. Implementing FIFO in Spartan-II
  182. Re: Help ! compxlib Error " mti_se not found" while Bulding XILINX libraries for ModelSim SE
  183. Re: WebPack ISE and Norton Anti-virus
  184. Re: Free FPGA samples anywhere?
  185. Convert Jedec to logical equations
  186. Please help me!!!!! ModelSim question...
  187. fixed point divider help
  188. Max finding
  189. Q:epax1 dma?
  190. Re: DA FIR filter vs. MAC FIR filter
  191. PCI Clock Issue
  192. Virtex2pro "Bufg Exclusivity"
  193. Asynchronous clock switching circuits vs. BUFGMUX
  194. Re: Problem configuring Cyclone
  195. Re: parallel port and cyclone?
  196. Verlog 2001 signed numbers
  197. Re: quetions about configure altera fpga(apex20k) using ppa scheme
  198. Re: What is the context switching time
  199. Re: Free FPGA samples anywhere?
  200. Re: Free FPGA samples anywhere?
  201. Re: Free FPGA samples anywhere?
  202. Multi-clock / clocking counter
  203. Re: Altera ACEX 1K IOE
  204. How to listen to music through an FPGA pin?
  205. Re: Why can't Xilinx DCM's regain lock without a RESET??
  206. FPGA minimum operating frequencies
  207. Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
  208. Dini DN3000K10S board for sell
  209. Xilinx bit files
  210. Re: Thinking out loud about metastability
  211. Re: Which Adder?
  212. Re: What is the context switching time
  213. Re: Reusing CCLK line after configuration for Spartan-II
  214. Re: Interfacing to pc parallel port?
  215. Re: Enhancing PAR with FPGA floorplanners
  216. Re: TIG Constraint
  217. Re: TIG Constraint
  218. Two near-identicial clocks?
  219. Re: What is the context switching time
  220. Re: Thinking out loud about metastability
  221. Re: EDIF input to Xilinx ISE
  222. [ann] Microblaze uClinux Demo released
  223. Re: Signal within block
  224. ISE Foundation 4.1i compatibility
  225. custom memory array implementaion
  226. Which software from Xilinx
  227. VHDL for FPGA VME Slave
  228. Problem with Modelsim Lisence server...
  229. Skew on a clock tree on a virtex II : what is the good figure ?
  230. FPGA/DSP Expert - business partner for innovative FFT
  231. PCI on Virtex II Pro (corrected)
  232. PCI on Virtex II Pro
  233. Re: Quartus II and fixing hold timing
  234. XILINX FPGA project
  235. Actel Core PCI
  236. Re: Xilinx Platform flash prom price
  237. Performance of STAPL player on embedded systems
  238. Error please Help
  239. Limitations of Quartus II V3.0 Web
  240. Virtex: Foundation 3.1 Error
  241. Re: Xilinx ISE error
  242. Update on Virtex II Pro Linux
  243. Xilinx DLL driving multiple off chip clocks
  244. Datasheet for National PAL20L10
  245. Re: speeding up quartus
  246. Nios Clock Frequency
  247. Non volatile implementation of Xc2s100
  248. PalmChip Patent
  249. Yet another modelsim problem
  250. Earn $500 to $700 per Week Downloading FREE Software Een