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  1. Spartan-3 non-ES availability, and misleading pricing info
  2. xilinx System ACE solution
  3. Configuration Blues
  4. Blocks RAM in HandelC
  5. 3rd party pci dma engine
  6. Looking for Hot 2 Boards
  7. pci protocol analyzer
  8. wincupl, winsim documentation?
  9. wireless test board
  10. explain the vhdl code
  11. explain the vhdl code
  12. Internship/Co-op
  13. develop a state diagram for the DTE VHDL code
  14. vhdl code
  15. Running Quartus II on ReadHat Linux 9.0
  16. Virtex-II Pro ML-300 Evaluation Platform
  17. Virtex-II Pro ML-300 Evaluation Platform
  18. tektronix 308 data analyzer
  19. Ph.inisheD.
  20. ICAP Virtex2
  21. To our future engineers, smart and otherwise...
  22. Xilinx XAPP265 and 800Mb/sec data input....
  23. Hot Swap Considerations
  24. Powersupply virtex 2 and spartan 3
  25. Unsupported predefined attribute
  26. Partial/ Dynamic Reconfiguration Virtex 2 pro- does it have any help at all
  27. Partial Reconfiguration
  28. simple project needed
  29. USB Core (Japanese Version) Revisited ;o(
  30. Altera mySupport
  31. DCM driving multiple OBUF's ... skew in between ...
  32. Multiple Positions - Reconfigurable Computing
  33. Electronic Dice ( 3 die ) In VHDL
  34. SpartanXL
  35. Universities that focus on IC design
  36. How to program an XC5210
  37. newbie linker script question
  38. Picojava FPGA and Development board
  39. problem with XC18v01 and Spartan XCS20XL
  40. FPGA/CPLD With Analog Functions?
  41. Xilinx Logic Handbook
  42. Pass transistor logic in a FPGA
  43. Xilinx "Programming failed" message
  44. mp3 project
  45. ByteBlasterII
  46. Clock doesn't seem to work on Xilinx CoolRunner XPLA3
  47. Debugging software in an ACEX device with Nios 32 via JTAG
  48. Please Help: Looking for XC3064 PLCC-84...
  49. PCI-X bridge from Xilinx LogiCORE and half bridge
  50. EPC16 will not Flash Program
  51. Quartus 2.2, SOPC builder and leonardo
  52. ISE6.1i RPM's, Multipliers and grids
  53. ISE6.1i Floorplanner
  54. How to select a FPGA
  55. PCMCIA FPGA Card
  56. PCMCIA FPGA Card
  57. finding delay
  58. XST Timing report
  59. Spartan-IIE Serial vs. JTAG configuration results in different functionality
  60. Quartus help with package declaration
  61. video effects eval boards
  62. FPGA Editor: Macro(Xilinx)
  63. RAM in Xilinx Spartan II
  64. from jedec to schematic ??
  65. Questions on Function Approximation (using FPGAs)
  66. Virtex-II Pro Core Voltage on ML300
  67. Questions on Function Approximation (using FPGAs)
  68. VCC's HOTman
  69. Xilinx XC2S50: Unable to configure through slave serial mode
  70. Problems with PCI-CardbusCard (interface is an FPGA) on Windows
  71. FPGA/PLD Reliability: High Speeds and Advanced Processes
  72. Inferring an accumulator using Verilog on Xilinx Spartan 2e
  73. pci-x133 to parallel pci-66
  74. cupl language reference?
  75. TRANSEDA VERIFICATION NAVIGATOR 2003 (WIN/LINUX) - new !
  76. Why no synthesis?
  77. Initilization of block rams to create rom
  78. News Test
  79. Where is the logic?
  80. Quartus II simulation question.
  81. Quartus, JTAG, Programming Hardware
  82. Spartan 3 pinout typo?
  83. Floorplanning, Routing, FPGA Editor
  84. Placing FF's Relative to RAMB4s (xilinx)
  85. syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVIDE_BY_2
  86. 5V Tolerant Spartan 2
  87. Xilinx dedicated multiers vs multipliers in slice fabric
  88. Jtag
  89. Implementing a fast cache in Altera Cyclone
  90. use of radix-2 ffts
  91. Visualizing VHDL
  92. Programmimg Altera serial configuration devices
  93. Xilinx DCMs, DDR, CLK0, and CLK180
  94. ASIC/FPGA programming
  95. EAGLE v4.11 Professional *Bilingual* - Cadsoft (Windows, Linux - new !
  96. Avnet Xilinx Virtex II Development Board - getting started
  97. BF957C Application
  98. Re: beginner - exisit some free schematics programmer for fpga ?
  99. More RPM / RLOC fun
  100. Installing Xilinx 6.1 under Linux
  101. ise 5.2 sp 3 for spartan 3
  102. Need a temp, p/time XILINX Guru; must be local, in San Jose CA
  103. RLOC specification
  104. SDRAM types and availability
  105. Design question (Working with Altera EPXA1F484C1)
  106. Problem with PCI cards
  107. Problem with PCI cards
  108. synplify vqm not able to fit in Quartus
  109. Should I worry about metastability
  110. Timing from 1x to 2x and back
  111. How To: 3-input NAND gate using ACTEL ACT 1 logic module
  112. Free timing diagram drawing software
  113. Reusing code (Altera Quartus II 3.0)
  114. Aldec Riviera v2003.06.1059 WinNT2kXP - new
  115. Simple I2C slave model (IO expander)
  116. Linux support in SDK 6.1i
  117. Interesting article about FPGAs
  118. large integer support in GNUPro for Altera Nios software development
  119. CLOCK_SIGNAL constraint XILINX
  120. Xilinx courses
  121. Virtex XCV300 Board for sale on e-bay
  122. Graphics rendering revisited
  123. Apology to Martin Erudjian
  124. MicroBlaze size
  125. Quartus II tutorial vs the real world
  126. MENTOR_GRAPHICS_LEONARDO_SPECTRUM_V2003B, MODELSIM_SE_PLUS_V5.7F,NATIONAL_INSTRUMENTS_DIGITA L_WAVEFORM_EDITOR_V1.0,CST_DESIGN_STUDIO_V2.3, SYNOPSYS_FPGA_COMPILER_II_V3.8,SYNOPSYS_STAR-HSPICE_V2003.09, XILINX_CHIPSCOPE_PRO_V6.2i,XILINX_SYSTEM_GENERATO
  127. Safe state machine design problem
  128. High-performance workstation
  129. CUPL documentation?
  130. Evaluation time of Emac Core?
  131. Host-PCI Bridge
  132. ISE 6.1 Dies Out of the Gate
  133. LVDS_25_DCI : Top Ten List
  134. Good VHDL/Verilog editor?
  135. Any word on the V2Pro-X?
  136. Looking for recent Altera Quartus Verilog synthesis experience
  137. Parameterized Multiplier in Xilinx FPGA
  138. Limitations of Xilinx coregen or limitations with using Xilinx primitives in synthesis.
  139. Automatic I/O voltage sensing (as XILINX ParallelCable IV)
  140. Any chance to buy Cyclone?
  141. DP RAM infering
  142. Interface Between National Semi Channel Link TX AND Virtex-II
  143. CADENCE ORCAD UNISON SUITE PRO V10.0 - new !
  144. Postal Lottery: Turn $6 into $60,000 in 90 days, GUARANTEED
  145. Digesting runs of ones or zeros "well"
  146. New version of HDLmaker available
  147. Implementing multiple registers with one single input output bus and address select in VHDL.
  148. Timing constraint for BUFG?
  149. ISE WebPack 6.1 Impact problem
  150. Reconfiguration via SelectMap on the RC1000
  151. doubling clock rate does what to power consumption?
  152. PCB VERIBEST 1998 - 2002
  153. Logic Analyzer for FPGAs
  154. nallatech ballynuey board
  155. Configuration Clause, XST
  156. c++ lcd device driver 2vp4
  157. Xilinx XST 6.x and Verilog-2001?
  158. Is Xilinx Webpack 6.1 help crippled?...
  159. Frustrations with Marketing
  160. Bit error rate
  161. Anybody have any experience with Altera Stratix 840 Mbps LVDS?
  162. ByteBlaster with USB<->PP adapter?
  163. Xess' XSA-50 Audio Playback / SDRAM
  164. USB Core (Japanese Version)
  165. newbie to FPGA
  166. development-tools under linux for altera excalibur
  167. Spartan 2e implementation
  168. Xilinx configuration
  169. using the FALLING constrain with cores (coregen)
  170. Spartan 2e implementation
  171. Memory Handling in Altera Cyclone devices
  172. FPGA : Partial reconfiguration of virtex2
  173. Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
  174. Counting ones
  175. Virtex-II Pro Equations for Finding a Bit Location
  176. Sparten-IIE Configuration (Slave Parallel Mode)
  177. ISE: Parallel Processing
  178. OT: spam poll
  179. Implementing Bidirectional pins
  180. Can I use pullup/pulldown to bias LVDS input?
  181. FPGA implementation of a lexer and parser - feasible?
  182. Xilinx ISE 6.1 Clocking Wizard - no hdl generated?
  183. Xilinx: LOC'd IO internal to VHDL Module
  184. FF with CE doesn't synthesize correctly by XST?
  185. Xpower report
  186. Partial Reconfiguration, ISE 6.1
  187. your opinion about Avnet (Silica) VirtexII Pro evaluation board
  188. pullup on inputs
  189. virtex2p power consumption
  190. How to change "X" to "0" or "1" (VHDL) ?
  191. NIOS and OCI
  192. Reducing Clock Speed
  193. Nanometers, Gigahertz, and Femtoseconds
  194. Strange synthesis behavior from Quartus II 2.2
  195. [ANN] New Prototyping boards speed Spartan-IIE FPGA development
  196. Quartus Usability Feedback
  197. Graphics rendering
  198. chipscope pro and jtag
  199. Transition from Virtex-E to Virtex-II
  200. Synchronous Binary counter question.
  201. on the fly Reconfig
  202. Free WebPack 6.1i Download Available Now for Spartan-3
  203. Speed of various elements in the spartan3
  204. Portable computer for FPGA/CPLD tools
  205. Reading from FPGA Issue
  206. WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
  207. Install problem RedHat 7.3 ISE 6.1i - no space available
  208. Regulator for Spartan 2
  209. Accessing local GSR net of a Spartan-II
  210. Corrupt Xilinx 18vxx poms
  211. New to VHDL for Xilinx
  212. IEEE 1284 Core for Xilinx
  213. PPC access to PROM using Virtex @ pro
  214. Location constraint
  215. FPGA RESEARCH FSK
  216. Added Keyboard controller to C-NIT
  217. DCM virtex 2 doesn't lose lock
  218. USB 1.1/2.0 Implementation
  219. LUT and Registers in Xilinx Virtex 2
  220. Cheapest programmer for a ICT 7572J Peel device
  221. Re: Configuration Options:
  222. Re: Configuration Options:
  223. Synchronous counter enable pulse length
  224. FPGA implementation in (V)HDL
  225. Moderator of comp.arch.fpga
  226. EDK 3.2: timing constraint for CLKDLL
  227. Regarding XC6216
  228. 1024 POINTS FFT V2.0 Xilinx Core
  229. Italy is out of FPGA world?
  230. show-ahead FIFOs
  231. LVDS in Xilinx (Spartan-3)
  232. ORCA fpga?
  233. Questions about XPower
  234. Xilinx Impact bitstream compression
  235. DigiLab2 Spartan 2 : Can't download..
  236. Some question about using FPGA
  237. NIOS: plugs without an uart?
  238. Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
  239. Parallel JTAG cable on a USB-only W2K laptop?
  240. Re: hardware image processing - log computation
  241. ISE 6.1 and Redhat 9
  242. Bitstream compression
  243. Xilinx Spartan 3, SelectMap, Mode pins, Dynamic Reconfiguration
  244. HDL Bencher for ISE5.1 Version
  245. VHDL and ModelSIM question
  246. Reconfiguration, Spartan 3, Compressed bit stream, ICAP
  247. divide by on spartan3?
  248. High Bandwidth Virtex II boards
  249. FS: IKOS NSIM 64 Simulation Acceleration Hardware
  250. Using LUTs for array of coefficients