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  1. Newbie Question about Block Ram & Xilinx ECS
  2. More basic questions about Spartan 2 IOB
  3. Altera's EPCS programming algorithm
  4. Do I need to connect all Vref in a bank together?
  5. Electric Copy Board (White Board) by Quartet Ovonics Webster model TS 600
  6. Inferring Dual Port Block RAM
  7. Stratix & PLL
  8. PCI Slot Expansion
  9. Color STN LCD controller
  10. getting started in FPGA
  11. FPGA Device Utilization
  12. Reading back SRAM content via JTAG?
  13. Altera MAX3000 device required.
  14. Writing Blockrams in VHDL
  15. Xilinx UART Macro ERROR???
  16. VIRTEXII IO problem
  17. How to bring PLL's output to Pin_F1
  18. unknown devices in JTAG chain
  19. _
  20. testing
  21. Xilinx Virtex2 tristate support
  22. Reading O value
  23. Archiving Projects
  24. SystemC Implementation
  25. SystemC Implementation
  26. linker script
  27. Will XPLA3 phase out?
  28. Frequency Doubler - VHDL/Verilog
  29. Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
  30. VHDL code for an mj2 parser.
  31. System generator and Microblaze
  32. Local nodes are not visible anymore after simulation (Altera Quartus II )
  33. Putting TNM on a FF inside vhdl
  34. Need to verify an ATA/ATAPI-6 device
  35. Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
  36. None
  37. About the purchase of XCF01s
  38. DCM input clock
  39. How to visit the files in CF cards
  40. XILINX Foundation Series 3_1i Problem with installation...
  41. Logic implementation in SRAM/OTP FPGAs
  42. Code for accessing CF cards on Cyclone dev.board
  43. Multiple clock domains in a FPGA (using DLL's)
  44. Multiple clock domains in a FPGA (using DLL's)
  45. DLL usage, multiple clock domains on FPGA.
  46. Transforming vector position to binary value
  47. Are modules that are not floorplanned still functional?
  48. fitting Xilinx CPLD - I/O Pin Termination
  49. Layout examples
  50. "clean" or "unprotected" versions of AHDL2X, SYNTHX from Xilinx (ABL2XNF sub tools)
  51. Reverse engineering an EDIF file?
  52. Implementing a very fast counterin VirtexII
  53. Xilinx SelectMAP configuration
  54. Enumeration by Host Controller
  55. Unconstrained net to DLL's
  56. How to create a look up table for a RAM application
  57. VirtexII-Pro: Why is ICAP slower than SelectMAP?
  58. CF card problem in Virtex-II Multimedia Board
  59. ISE 5.2 to 6.1
  60. Home grown CPU core legal?
  61. ASIC vs FPGA
  62. None
  63. Watch the correction patch
  64. 0.13u device with 5V I/O
  65. Capturing Video with RC200E board of Celoxica
  66. FPGAs and DRAM bandwidth
  67. PCI - X Boot up
  68. External Modules and FPGA Primitives
  69. FPGA & handling reset of a logic block while running
  70. spartan 3 queries
  71. xhwif for admxrc2 board (alpha data)
  72. ispLSI-2064 -- how to decompile jedec file to ldf file?
  73. ASIC speed
  74. Impact, SVF, assumed TCK frequency?
  75. FA: XCV800 BG560 FPGA ( 51 pieces
  76. FA: XC18V04 Flash Proms
  77. Arithmetics with carry
  78. Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
  79. Creating a vector out of other vectors
  80. latch and shift 15 bits.
  81. Virtex2Pro--ppc405-FPGA communication
  82. Smart card ISO 7816 and NIOS Altera
  83. ISE : Synthesis process hangs
  84. Infer DDR registers from RTL?
  85. Programmer's unpaid overtime.
  86. Announcement
  87. Linux and FPGA compatibility
  88. Virtex II DCM & ZBT SRAM
  89. Problem in Implementation Costraints
  90. parameter in top module in XILINX ISE 6.1.02
  91. microblaze exceptions
  92. FPGA Prototyping Board
  93. device progamming hardware found; device programming software sought
  94. Xilinx platform flash VCCO/VCCJ
  95. Video Scan Conversion Rate - Camera Input to DVI Display Output
  96. Voila: Nedit macro to produce verilog module instantiations
  97. help with 120MHz comparator
  98. Silly ML300 question...
  99. I/O on current FPGAs - deserialise first ??
  100. DCM recover after interruption of input clock
  101. Prototyping board with 4+ MB SRAM?
  102. Re: Searching for 802.11a/g implementations
  103. X-HDL 2003
  104. Tools Tree
  105. MODELSIM_SE_PLUS_V5.7F, ModelSim_SE_Plus_v5.7G,MODELSIM_XILINX_EDITION_II_ V5.7C, XiliNX.Embedded.Development.Kit,XILINX.ISE.V5.1i, XILINX.ISE.V5.2I, XILINX_CHIPSCOPE_PRO_V6.2i,XILINX_ISE_V42I, XILINX_SYSTEM_GENERATOR_V3.1,XILINXFOUNDATIONSERIE SISE33I
  106. 5 input LUT in virtex
  107. Defect and Fault Tolerance Material
  108. Using the Virtex Block Select RAM+ Features
  109. synplify Pro 7.3.1
  110. Altera "my support" :-(
  111. Xilinx - Multi Volt Interfacing
  112. Building the 'uber processor'
  113. Vendor supplied symbol/part models?
  114. Power-On-Reset from a xilinx
  115. Spartan II with Digilab board, IO communication
  116. VHDL Xilinx Flow Engine ERROR
  117. help ;lattice synario error
  118. Xilinx Weback 6.1i - Java Exception
  119. Video decoder and encoder IC's
  120. Using unused space on a PROM (configuration device) as an EEPROM
  121. Nios & external RAM
  122. WinCE driver for Wildcard from Annapolis Micro System?
  123. Convert verilog to VHDL??
  124. Shannon Entropy for Black Holes
  125. data recorder examples?
  126. Floating Point support
  127. Are there more I/O pins than I/O blocks?
  128. Microblaze & ucLinux for XSV800
  129. Essential hazards in CPLD's?
  130. Minimalist RS232 on Cyclone
  131. Address Mapping in 4K RAM Blocks in Altera Cyclone Devices
  132. Wishbone interface, FPGA newbie and advice
  133. TNM on Tristate buffers
  134. ANNC: WebPACK 6.1 tutorials
  135. Xilinx XC95108 Chip
  136. comparison of FPGA tools?
  137. TAP controller state vs PROG pin
  138. simulation stops preliminarily
  139. CLKFX problem with a Virtex II
  140. Hit Logic
  141. Accessing Ports of a "User to Interface Logic" on a Altera Nios
  142. VirtexII-Pro: Full Readback via ICAP/SelectMAP
  143. PicoBlaze for Altera (ACEX1K)?
  144. For sale: XCV1000E FG680 6C
  145. Some FPGA questions
  146. DDFS technique problem in generating a few clocks
  147. Questions that question????
  148. using extra eeprom space
  149. Electronic News Article on 90 nm soft error FUD
  150. Fatal Error obtained while translating in xilinx ISE 5.2
  151. Reconfigurable Computing Pointers?
  152. Xilinx PPC405 DCR Interface
  153. How to protect fpga based design against cloning?
  154. LogiCORE PCI-X question
  155. MicroBlaze : can I assign Boot BRAM address other than 0x0?
  156. Xilinx Spartan3: Price
  157. Xilinx Sparttan Fpga ON SALE. Wend.
  158. Virtex-II DCM frequency synthesizer
  159. How can I lock design with ISE 5.2?
  160. Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN
  161. Static 1 and 0 Hazards
  162. Trenz-electronics (spartan2 development board) help?
  163. What's a good book on FPGA CPU design?
  164. How to import QuartusII simulation waveform (vwf) and block design file(bdf) to the Word (.doc)
  165. Re: View the signal in the analog domain ModelSim
  166. Input pins that are driven but not used
  167. Question about post-PAR simulation
  168. Electronic Dice VHDL Program
  169. BoardScope
  170. Memory for FPGA based LCD Driver/Controller
  171. Altera ACEX1K configuration and initialisation
  172. Initializing inferred components with Xilinx ISE Foundation 6
  173. ChipScope problems
  174. Does a dont_use statement exist?
  175. Picky WebPACK 6.1
  176. SDRAM Controller
  177. Verilog Program With A Problem
  178. Virtex2 DCMs
  179. Hex display with Quartus simulation
  180. Modeling hardware in Matlab/Simulink (delay, etc.)?
  181. Searching for 802.11a/g implementations
  182. Picoblaze development tool
  183. programming Altera AS Configuration Device without Byteblaster II
  184. not replaced by logic error
  185. Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded interpreter (www.hightech-td.com)
  186. Pass transistor logic and multi-valued logic in a FPGA
  187. Xilinx tsi report confusion
  188. [ANN] Confluence 0.7.1 Released
  189. Searching for 802.11a phy IP
  190. Are clock and divided clock synchronous?
  191. interpreting OFFSET
  192. OPB write actions
  193. problem with Xilinx
  194. Another strage timing problem
  195. Anyone with old Foundation?
  196. Fatal error while compiling code
  197. Strange Timing Problem
  198. Altera cyclone circuit board indicator
  199. I Need to Generate a NTSC Signal - Help!
  200. Any problems with Xilinx 6.1i ISE?
  201. The Luddite Needs Reference Books...
  202. Timing analysis
  203. Timing analysis
  204. Amplify under Windows server 2003
  205. EMC/SDRAM
  206. PPC boot
  207. Cool test bench generator for testing some devices which describe by Verilog or VHDL
  208. NIOS simulation with modelsim -> strange behaviour
  209. VHDL Souce Code Beautifiers
  210. Virtex II MJA
  211. Block Ram clocks
  212. Beginners advice for selecting an environment for FPGA design
  213. Verilog Encounted Errors
  214. Job postings
  215. Strange error in Quartus II 3.0
  216. Sort of Running Quartus II on SuSE Linux 8.1
  217. 74 logic to CPLD. how easy for a Newbie?
  218. Structure of the Embedded Multiplier?
  219. bitstream compatibility
  220. Altera programming problem
  221. please help, modelsim does not simulate
  222. Quicklogic DeskFAB Programmer
  223. BIT files
  224. What is Spartan3 DLL per tap delay
  225. Subroutine in VHDL?
  226. Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
  227. Re: BGA packages in high vibration environments
  228. Power calculation using Xpower
  229. Waveform Interpreted
  230. USB 2.0 controller using ISP1581 device
  231. Virtex CLB
  232. Several Quartus II 3.0 questions
  233. CPU vs. FPGA vs. RAM
  234. ignoring SPO output on dual port ram
  235. Running Quartus II on ReadHat Linux 9.0
  236. Altium DXP for designing Xilinx FPGA
  237. Re: BGA packages in high vibration environments
  238. Signed Multiplication in a Virtex-II Multiplier.
  239. ECRTS 04 -16th Euromicro Conference on Real-time Systems, CataniaSicily
  240. Is it possible to define a preprocessor macro in Xilinx ISE
  241. Anyone try the Gameboy FPGA system?
  242. ISE5.2 to ISE6.1
  243. How to get Synplify 7,0 Pro and Xilinx EDK 3,2 work together.
  244. program a Lattice MACH211
  245. microblaze data transfer
  246. Error Message when using process with wait-statement in testbench
  247. Xilinx Slice and Altera ...?
  248. LUT and latch in the FPGA
  249. MICROBLAZE: executing program from external memory
  250. VFDs