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  1. a question about flex10 configure
  2. Emulation on PRODESIGN Platinum Edition
  3. VHDL-Xilinx-Simulation (signal not connected to port) ?
  4. Xilinx Johnson counter Verilog example bug?
  5. Problems with Xilinx ISE6.1i P&Rs for Virtex II
  6. pcix core in XC2VP7
  7. Net name convention for Xilinx UCF files.
  8. Avnet Virtex II Pro Dvpt board : linux drivers ??
  9. A simple horizontal frequency doubler PLL for TV line doubler.
  10. Hyperthreading vs. Dual proc
  11. Spartan II Block Ram
  12. WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
  13. How to use differential clock pin of SpartanIIE?
  14. Parallel Cable 4 & Linux
  15. V2Pro floating point
  16. predictable timing for xilinx cpld?
  17. IEEE SOC Conference Call for Papers (Deadline April 16 2004)
  18. Spartan3 availability
  19. powering spartan IIe
  20. www.micron.com VHDL models gone ??
  21. Xilinx IOSTANDARD for PCI-X 100MHz interface
  22. CRC-32 in spatan-3
  23. FIR Filter cores for Virtex-][
  24. www.fpga-faq.com
  25. Exporting a EDK design to Project Navigator
  26. Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
  27. interfacing a WishBone IP core to a CoreConnect bus
  28. VHDL comments in Vim?
  29. Initialising LPM_ROM
  30. Xilinx .ucf
  31. What is this ASMBL thing from Xilinx?
  32. From ASIC to FPGA these days
  33. Multi-FPGA PCI board recommendations???
  34. Altera Stratix 80: How to divide a bits stream to even bits streamand odd bits stream
  35. Rocket IO testing
  36. PIN naming confusion xilinx spartan 2E XC2S200E
  37. download ise foundation
  38. Extracting timing from a demo board (V2MB1000)
  39. .elf to .bin file for microblaze
  40. FLEX 10K50E, which software support it?
  41. How LVDS Drivers kills?
  42. Help w/ WARNING:Xst:1868
  43. multiplier,CLK-insufficient RECOVERY time after async CLEAR
  44. WORK IN PROCESSOR BASED FPGAS - VERTEXII PRO
  45. advantages of ethernet MAC ip core
  46. Question about filters and verilog etc..
  47. Question about EDK and C functions
  48. MAX104 vs. XC2VP
  49. byte order microblaze
  50. Analyzing the design with ChipScope Pro
  51. EDK, reset module, interrupts
  52. Initialising LPM_ROM
  53. Microblaze interrupts
  54. Spartan-IIE TDO and CCLK pin status
  55. 16-bit sdram and 32-bit opb bus
  56. ASCI Winterschool on Embedded Systems
  57. Programming Altera MAX 7000E
  58. Xilinx 6.1i Tools and Newer Redhat Linux OSes
  59. Xilinx 6.1i tools on Newer RedHat OSes
  60. Xilinx 6.1i on Redhat Enterprise or Fedora
  61. stopping XMK (at microblaze)
  62. Which PCI version on my motherboard
  63. Latches inferred ?
  64. ISE5.2i strange behavior in PAR (command-line)
  65. Re: Too many signals [Xilinx Foundation 4.1i]
  66. spartan2 pin LOC strange error
  67. numeric_std and signed "/" operator
  68. Soldering of FPGAs
  69. Manufacturing Tests
  70. programming with sockets on Xilinx Virtex2Pro
  71. Maximum bus speed of APB.
  72. ASMBL - hmmm
  73. FIFO design
  74. Embedded Powerpc in xilinx
  75. Xilinx Spartan II pull-up, simple questions
  76. ISP for XCR3256XL
  77. BUFT resources in Spartan II
  78. w
  79. Too many signals [Xilinx Foundation 4.1i]
  80. Q:Altera's excalibur device
  81. Hold violations
  82. USB basic doubts
  83. Finding Multicyle Paths in a Design
  84. clock recovery from HDB3 data
  85. Quartus-II question
  86. Skew between the output of a DCM ?
  87. NIOS: Running code from flash
  88. How to assign inferred logic to resource in Quartus
  89. Mixing simulation of behavioral and synthesized code
  90. Position: custom mixed-signal Application Specific Integrated Circuits (ASIC's).
  91. Verilog-2001 `define expressions?
  92. MicroBlaze - how much memory?
  93. How to explicitly call out cell elements in Altera Stratix?
  94. Block RAM simulation VII
  95. Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial design
  96. "PIPELINE MODEL" constant in EDK 6.1
  97. Dual-port and single-port BlockRAM instantiation
  98. VHDL-Testbench-Simulation in QuartusII
  99. XILINX FPGA: DCM locked Signal
  100. VHDL: Different direction buses
  101. Floorplanning techniques
  102. Xilinx DDR output with tri-state....
  103. Using FPGA Editor to introduce PULLUP and PULLDOWN
  104. process table for XMK
  105. Need a few tips working with an Xilinx FPGA
  106. Ideal Development Machine Specifications
  107. Ideal Development Machine Specifications
  108. Spartan-IIe CCLK after config
  109. Synchronization between CPU-clock and FPGA clock.
  110. post-synth. with webpack
  111. Hold violation and PLL
  112. CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD)
  113. Partial Reconfiguration:Par fails during Assemble
  114. Command line in Windows?
  115. DPRAM - DIN, DOUT
  116. Spartan IIE daisy chain problems
  117. 1.2V Voltage Regulators for Spartan III
  118. Xilinx Virtex-II: DCM int & ext feedback
  119. Problem using JBits 2.8 with (esl) RC1000-PP
  120. OFFSET OUT with phase shift in DCM
  121. Modelsim 5.8 corrupt call stack when adding signals to wave window.
  122. Triscend Fastchip software under Windows XP?
  123. increase NIOS processor clock speed on APEX20K200E device
  124. Quartus generics and vhdl
  125. Design analyse methods
  126. ngdbuild, edif2ngd Pipe ended error
  127. SPARTAN-II, busy signal
  128. Exact Timing Constraints vs. Over-Constraining
  129. CoreGenerator
  130. debugging microblaze with xmd
  131. Functional Simulation QuartusII
  132. about digilent board
  133. jitter in Virtex2 DCM
  134. XC2VP70 FPGA board suggestions
  135. MPEG2 decoder
  136. what's the problem?
  137. Digilent Inc.
  138. how to create timing report for all nets?
  139. problem with RS485 or RS232
  140. Timing Analyzer - delay to die pad or package pin?
  141. [VirtexII + DCM + newbie] problems with the clocksignals from DCM
  142. Any integesting article about PLD for short presentation
  143. modular design flow in Xilinx ISE 6.1.
  144. Xilinx FPGA Clock Skew
  145. PCI LogiCORE with ISE 5.2
  146. overshoot problem of EPM7128S
  147. Phy IP for Giga ethernet for Virtex -II Pro
  148. Xilinx ISE 6.1 external editor
  149. IDE Ultra DMA on a SPARTAN II (corrected version)
  150. IDE Ultra DMA on a SPARTAN II
  151. FS: Vitex-II / APEX20K
  152. external sdram and gdb tool
  153. Re: Soft-core processor construction
  154. Input pins without Vcco supply-- Virtex-II
  155. Quote from Xilinx re: XPLA3
  156. what is the fastest speed that FPGA deals with CPU?
  157. XVPI
  158. memory
  159. Can there be 2 loops in one process
  160. area constraints
  161. running from external memory (microblaze)
  162. using xilkernel
  163. programmable fir and simulation
  164. Soft-core processor construction
  165. Slightly unmatched UART frequencies
  166. ANN: Tyd-IP Code Generator ....VHDL for DSP
  167. ANN: Tyd-IP Code Generator ....VHDL for DSP
  168. 5V I/O with 1.8V Core
  169. Reconstructing source code from JED file
  170. Differential terminations in Virtex2 Pro.Attempt II!
  171. Dual port RAM for Xilinx
  172. How many dedicated clock pins EP20K1500EBC652 device?
  173. MDD file
  174. Has anyone had any luck complining examples for a Virtex-II multimedia board
  175. store program in external sdram
  176. Xilinx ISE 6.1i+SP2 And Modelsim 5.8
  177. Laptop without serial/parallel port
  178. Aurora_401 reference allows 8B/10B bypass?
  179. LF: Affordable Development Board
  180. any FPGA design for video frame memory control?
  181. Generating core using .mif file
  182. Differential terminations in Virtex2 Pro.
  183. Xilinx WebPack and Linux/WINE
  184. Implementing submodules with their own constraint files
  185. FC II & Generic
  186. Xlilinx (xc2vp30-5fg676)
  187. Virtex2Pro Internal Config. Access Port
  188. Undocumented units in Virtex (I assume in Spartan-II too)
  189. ERROR:Pack:1107 - ISE 6.1
  190. XC9500 design does not fit into Coolrunner
  191. verification vs validation
  192. graphic card accelarator vs. FPGA: which is better for the following task?
  193. How to set 'set up time' in a Quartus Tool for a PCI Device
  194. Xilinx legacy situation
  195. vhdl construct problem
  196. Quartus II Node Finder
  197. Xilinx Microblaze SDRAM burst access
  198. Altera Max 7000 cpld's
  199. avoiding GCLK
  200. Virtex Benchmarks
  201. Xilinx UCF file conditional includes ?
  202. Small PLD choices
  203. Apex power calculator
  204. How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
  205. State Machines....
  206. 400 Mb/s ADC
  207. Embedded Development Kit + performance
  208. Xilinx microblaze : SRAM external mem controller
  209. interrupt handler for microblaze system
  210. XPS - Compiliing Core Generator's components
  211. Where and How to get Nvidia Geforce 5600 public desigh graph
  212. SDRAM-Controller XAPP134
  213. regarding clock routing
  214. Does anyone know anything about DC-FPGA?
  215. Anyone use HDL as design tool for PCBs?
  216. XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
  217. Altera Stratix synthesis error
  218. Xilinx DCM LOCKED signal valid after input clock returns?
  219. CFP: EH-2004 Second Call for Abstracts
  220. CPLD : Generating reset signal
  221. Problems Configurating MicroBlaze into RC200 board
  222. PCI interface with attached PLD
  223. SPI 4.2 Core perceptions and Power
  224. HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
  225. %age occupation of interconnect resources
  226. None
  227. microblaze as submodule
  228. using multilinx from ISE to download a bit file
  229. xilinx platform flash question
  230. Memory Initialization: mif, coe, hex, etc,
  231. Xilinx Design entry via Schematic Capture - What tool to use ?
  232. Acek 1K - Quartus II - timing issues
  233. Virtex-E 2000 price
  234. Virtex II multipler performance
  235. Is this a good starter kit?
  236. Virtex-E 2000 price
  237. ISE 4.2 sp3 (Solaris)
  238. Tool for connecting modules,download free,quick demo
  239. Architecture desing using national serializer and deserialiser
  240. Synplify Pro/ISE adder carry chain - interrupted
  241. Altera's altsyncram MAXIMUM_DEPTH
  242. Altera synthesis of registered signals ???
  243. Active-HDL 6.1 pricing
  244. ISE5.2 on solaris, can't use promgen
  245. SRL16 as synchronizer
  246. Vertex-II configuration in slave SelectMap mode
  247. ISE 6.1 with synplify : pin assignments
  248. Imagecraft ICCAVR & ANSI Standards compliance
  249. standalone IMPACT
  250. Looking for A3951SW parts