- Virtex II Pro, powerpc 405 and ucOSII
- Verilog 2001 indexed part select in XST 6.1.3?
- Xilinx old development tool
- Everithing you need
- Xilinx Spartan3 Timing Problems - Whats about the chips
- Anybody has any experience with Tarari Content processor?
- Spirit on Mars
- Synthesis errors?
- map gives yet another error!
- Soft failures (?) 9536XL
- MACH5 eval board - doc needed
- xilinx 70% tracking rule
- EDK - Desinging system with C++
- How can I have multiple drivers of one inout port?
- Reference Designators naming standard...
- Synthesis of Loops
- microblaze reg_addr and new_reg_value outputs
- yo
- References to good PCI boards and some newbie questions - please help!
- PowerPC and JTAG
- Xilinx design process....
- spartan3 power supply
- OT: liability insurance
- changing values in a fifo
- RocketIO evaluation
- Tristate buffer
- BIST FPGA testing - Applying a test vector
- ERROR:HDLParsers:164
- Small bit manipulation on two designs with routing differences...
- Non deterministic routing in Quartus 3.0 ?
- ISE 6.1 and Win2000 sp4
- Why doesn't NGDBuild recognize some UCF formatting?
- Good/Affordable Stater kits
- Help on [email protected] memory initialization file
- QUES: Where can I find Xilinx M1 tools
- Altera/Xilinx Distributor in Europe?
- QUIP ( advance)
- PIC17C756
- simulating
- Rocket IO Transceiver : Loss of Sync Signal Always high
- Trouble using ChipsCope Pro with MicroBlaze
- Help required on CoolRunner (XCR3256XL) In-System Programming
- How to handle top-level glue logic.
- Memory Initialization Files in Modelsim
- par problems with modular design for partial reconfiguration
- fpga4fun ethernet
- WTD: info on AMD palce22v10
- Avalon DMA problems
- Anisotropic filter
- 802.3 mii
- Downloading to an FPGA
- FPGAProto board is now available for purchase !
- fpga4fun
- Deriving 36MHz from a 40MHz crystal using DCM?
- Simulation Speed when using Xilinx DCM
- Spartan XC2S200 - how many BlockRAMs ?
- QUIP( Altera ) interseting But ?????
- Timing Simulation ModelSim / Quartus
- Block RAM
- Xilinx ISE 6.1 problem
- Impact of voltage variations on timings for an FPGA
- so nobody knows how to simulate Rocket IO using Active HDL ?
- Good software to experiment with VHDL
- Can XILINX run in multiple instances?
- Avnet Virtex-II Pro Development Kit Help
- mapper optimization
- WebPACK and foldback nands
- Spartan-3 VCCINT
- Power-up input value detection
- Simulating USB2.0Transceiver
- Hardware to test (FPGA-based) prototype?
- Error in Assembly stage.
- Can nios_gnupro support file system?
- Spartan-IIE as an ASYNC RAM?
- after the synthesis total logic elements are equal zero
- mapper optimization
- yo, Mr. FPGA Engineer
- DMA w/ Xilinx PCIX core: speed results and question
- Virtex 2 Pro : Rocket IO Simulation Problem
- Test
- timescale
- Please help with Xilinx ISE Schematic question
- Port mapping a Verilog component in a VHDL design
- Which version of ISE Webpack has FPGA Editor on it?
- Generating clock delays
- Gray encoding for FSM
- 1.8v SpartanIIE
- What does nios-run do?
- XC2V1000-5FG456C
- Faster than a speeding bullet...
- translating .jed files to equations
- Virtex II - LVDS_33_DCI?
- Microblaze simulation
- Installed Xilinx ISE6.1i on the Fedora
- Xilinx Decoder Position Open In Metro D.C.
- Can i get a sample XSVF file?
- How do I constrain this type of design?
- Simulation model of SRAM
- nios-build debug option
- How to explicitly call out cell elements in Altera Stratix (Follow-up)
- Nios memory
- logicore PCIX issue/question
- just a test
- Open source ARM, Version 0.1
- Error: (vsim-3341) Cannot open file
- simulating xilinx clkdll
- WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(15)
- 'universal delay' term in Xilinx parts
- Send Ethernet traffic from an FPGA
- Simulation model for UTMI available ?
- SPARK C-to-VHDL Synthesis tool now supports Windows & Xilinx XST
- Integer or Binary Vector?
- SPARK now supports Windows & Xilinx XST
- System Generator and Microblaze
- Making XAPP134 synthesizable
- V2Pro Rocket IO Primitive- Parameter and Port Settings
- using signal as clk source
- ANNOUNCE: Impulse CoDeveloper for MicroBlaze & Nios FPGAs now available
- Power plane assignments in a Xilinx PCI card
- to generate steps in phase
- IOB costraints
- The Fifo in xapp258
- Xilinx JBit v1.x
- fpga database?
- Why won't Xilinx document their code??
- pci-x core
- the pacer rep suggested these people as an alternative to exp
- Modify Memory after P&R in Xilinx Virtex2
- V2P7 Partial reconfiguration, FATAL_ERROR in par
- How to generate a CSA tree?
- Altera NIOS cyclone edition development board problem
- Error message in Mapping while using Xilinx ISE 6.1.03i
- Protecting Designs - any suggestions
- Altera Cyclone Programming device programming
- Altera Cyclone data is incomplete or messy
- image file reading in vhdl
- image file reading in vhdl
- PCB for FG456: layers
- Xilinx ISE6.1 Verilog `define macro?
- Programming and debugging the Altera Cyclone family
- Spartan-3 LC Development Kit from Insight (Memec)
- Altera Cyclone Serial Configuration devices.
- Dedicated CLK lines in CPLD
- What is wrong with my DCM experiment? How come the testbench won't simulate DCM1.
- ISE6.1 rom16X1 initialization INIT
- FPGA Size
- FLASH memory programming with Altera NIOS and same question for Xilinx
- Job offer: "Optimization on reconfigurable architectures"
- Spartan3 IOB without supply
- Newbie Question: No Vsim, Vlib etc in my ModelSim
- Anybody know what the REAL story is?
- New HDLmaker release available
- VSPWorks v4.5.1 (c) Wind River, visualSTATE v5.0.7.88 (C) IAR, LOGICDESIGN AND VERIFICATION V5.1 (c) CADENCE, other ...
- Verilog Benchmarks for FPGA research
- Large/Fast static RAM
- Readbackn on Virtex II Pro devices
- Dual Port RAM Block RAM using Core Generaot
- Improvement on the modular design methodology...
- ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
- Local constant (VCC & GND) for partial reconfiguration.
- Quantization levels of received symbol for viterbi decoder
- min propagation delay in xilinx cpld
- submodules with their own constraint files
- old articels of this newsgroup
- spartan 3 sample
- iMPACT error : Done did not go high.
- Wierd problem with Xilinx XC9572 ID code
- Xilinx ECS - connecting a single net to multiple bus lines?
- newbie question: speed grade + area constraint
- Tutorials for ISE and Quartus
- Synthesis in VHDL vs. Verilog
- DPRAM using the CoreGenerator, VHDL-example
- plb_sdram, timing error
- Xilinx Question
- Clock domains
- IP or Core
- SDRAM Controller timing problem
- FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus
- Generate the first interrupt for MB XMK
- Conversion of NCD files from 5.X to 6.1X, problem.
- Where do XPP290 places top-level logic when all three AREA_GROUPs have DISALLOW_BOUNDARY_CROSSING on them?
- Virtex and Spartan
- AFX BG560 board
- Simulating multi-chip design
- [newbie] How to get the value of active pins through JTAG
- readback spartan2e
- How do you initialize signals in VHDL?
- VirtexE DLL locked range
- Xilinx Virtex II Output Register
- Questions about guard bits in CORDIC algorithm
- Installation of Xlinx
- Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
- Winterschool on Embedded Systems (call for participation)
- XST cant compile with blaxkboxes.
- Where i can get the programming sequence of CoolRunner?
- Followup to those that downloaded SeaHDL/SimHDL
- fast mod (remainder) algorithm for V2?
- Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
- v2px70 available?
- Altera CPLD - Illegal assignment-global clock
- DCM Synthesis - Certify Planner Error
- FCCM'04 Reminder -- submission deadline Jan 19
- p160 connector
- maxplus 2 waveform simulation
- how to set the ISP mode for programming CPLD?
- Adding internal signals in MODELSIM
- How do I make use of local-clocks in a Virtex-2 FPGA?
- connecting tristates
- Do all the Vertex DCM outs use same global clock tree?
- Floating point in Nios SDK
- Xilinx Logicore PCI64 Problem
- System Ace - Flash card formatting
- rs-232 trouble
- is this a good idea
- Complicated clocking in an FPGA.
- HDL Bencher question
- C-NIT based complete SoC + FPGAProto preview
- Response to [email protected] on high level simulation
- please help! state machine
- Newbie Question: Compiling VHDL in Mentor Graphics
- Partitioning Problem in FPGA and Its Embedded PC Core
- help for Viterbi decoder design
- Virtex2Pro + SysGen
- Getting up-to-date libraries for timing simulation
- Question on partial reconfiguration flow...Must use EDIF flow?
- Newbie VHDL issue with CPLD
- boolean to std_logic
- A dilemma: which signal to use as a master?
- SOS : 4-bit binary divider circuit PLEASE!!!!!!!
- dynamic memory allocation NIOS
- FLEXlm reports
- virtex-II problems
- A difference between VHDL sources working
- This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
- How to use write flash on board?
- Spartan3 prices again...
- Xilinx Parallel cable
- Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
- Virtex-II Pro and DDR2 SDRAM differential IO
- [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
- Bus delimiter in iseWebPACK 4.2
- CHES 2004 - 1st CFP
- EDK oddity
- FPGA SRAM
- Anyone has the AMD flash AM29LV800B verilog model?
- LVPECL_33 to LVPECL_25 (virtex-II pro)
- Fast Fourirer Using Xilinx ISE
- Question regarding the sample design in XAPP290.
- How to get first bit '0' position in certain register?
- How to get first bit '0' position in certain register?