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  1. Virtex II Pro, powerpc 405 and ucOSII
  2. Verilog 2001 indexed part select in XST 6.1.3?
  3. Xilinx old development tool
  4. Everithing you need
  5. Xilinx Spartan3 Timing Problems - Whats about the chips
  6. Anybody has any experience with Tarari Content processor?
  7. Spirit on Mars
  8. Synthesis errors?
  9. map gives yet another error!
  10. Soft failures (?) 9536XL
  11. MACH5 eval board - doc needed
  12. xilinx 70% tracking rule
  13. EDK - Desinging system with C++
  14. How can I have multiple drivers of one inout port?
  15. Reference Designators naming standard...
  16. Synthesis of Loops
  17. microblaze reg_addr and new_reg_value outputs
  18. yo
  19. References to good PCI boards and some newbie questions - please help!
  20. PowerPC and JTAG
  21. Xilinx design process....
  22. spartan3 power supply
  23. OT: liability insurance
  24. changing values in a fifo
  25. RocketIO evaluation
  26. Tristate buffer
  27. BIST FPGA testing - Applying a test vector
  28. ERROR:HDLParsers:164
  29. Small bit manipulation on two designs with routing differences...
  30. Non deterministic routing in Quartus 3.0 ?
  31. ISE 6.1 and Win2000 sp4
  32. Why doesn't NGDBuild recognize some UCF formatting?
  33. Good/Affordable Stater kits
  34. Help on [email protected] memory initialization file
  35. QUES: Where can I find Xilinx M1 tools
  36. Altera/Xilinx Distributor in Europe?
  37. QUIP ( advance)
  38. PIC17C756
  39. simulating
  40. Rocket IO Transceiver : Loss of Sync Signal Always high
  41. Trouble using ChipsCope Pro with MicroBlaze
  42. Help required on CoolRunner (XCR3256XL) In-System Programming
  43. How to handle top-level glue logic.
  44. Memory Initialization Files in Modelsim
  45. par problems with modular design for partial reconfiguration
  46. fpga4fun ethernet
  47. WTD: info on AMD palce22v10
  48. Avalon DMA problems
  49. Anisotropic filter
  50. 802.3 mii
  51. Downloading to an FPGA
  52. FPGAProto board is now available for purchase !
  53. fpga4fun
  54. Deriving 36MHz from a 40MHz crystal using DCM?
  55. Simulation Speed when using Xilinx DCM
  56. Spartan XC2S200 - how many BlockRAMs ?
  57. QUIP( Altera ) interseting But ?????
  58. Timing Simulation ModelSim / Quartus
  59. Block RAM
  60. Xilinx ISE 6.1 problem
  61. Impact of voltage variations on timings for an FPGA
  62. so nobody knows how to simulate Rocket IO using Active HDL ?
  63. Good software to experiment with VHDL
  64. Can XILINX run in multiple instances?
  65. Avnet Virtex-II Pro Development Kit Help
  66. mapper optimization
  67. WebPACK and foldback nands
  68. Spartan-3 VCCINT
  69. Power-up input value detection
  70. Simulating USB2.0Transceiver
  71. Hardware to test (FPGA-based) prototype?
  72. Error in Assembly stage.
  73. Can nios_gnupro support file system?
  74. Spartan-IIE as an ASYNC RAM?
  75. after the synthesis total logic elements are equal zero
  76. mapper optimization
  77. yo, Mr. FPGA Engineer
  78. DMA w/ Xilinx PCIX core: speed results and question
  79. Virtex 2 Pro : Rocket IO Simulation Problem
  80. Test
  81. timescale
  82. Please help with Xilinx ISE Schematic question
  83. Port mapping a Verilog component in a VHDL design
  84. Which version of ISE Webpack has FPGA Editor on it?
  85. Generating clock delays
  86. Gray encoding for FSM
  87. 1.8v SpartanIIE
  88. What does nios-run do?
  89. XC2V1000-5FG456C
  90. Faster than a speeding bullet...
  91. translating .jed files to equations
  92. Virtex II - LVDS_33_DCI?
  93. Microblaze simulation
  94. Installed Xilinx ISE6.1i on the Fedora
  95. Xilinx Decoder Position Open In Metro D.C.
  96. Can i get a sample XSVF file?
  97. How do I constrain this type of design?
  98. Simulation model of SRAM
  99. nios-build debug option
  100. How to explicitly call out cell elements in Altera Stratix (Follow-up)
  101. Nios memory
  102. logicore PCIX issue/question
  103. just a test
  104. Open source ARM, Version 0.1
  105. Error: (vsim-3341) Cannot open file
  106. simulating xilinx clkdll
  107. WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(15)
  108. 'universal delay' term in Xilinx parts
  109. Send Ethernet traffic from an FPGA
  110. Simulation model for UTMI available ?
  111. SPARK C-to-VHDL Synthesis tool now supports Windows & Xilinx XST
  112. Integer or Binary Vector?
  113. SPARK now supports Windows & Xilinx XST
  114. System Generator and Microblaze
  115. Making XAPP134 synthesizable
  116. V2Pro Rocket IO Primitive- Parameter and Port Settings
  117. using signal as clk source
  118. ANNOUNCE: Impulse CoDeveloper for MicroBlaze & Nios FPGAs now available
  119. Power plane assignments in a Xilinx PCI card
  120. to generate steps in phase
  121. IOB costraints
  122. The Fifo in xapp258
  123. Xilinx JBit v1.x
  124. fpga database?
  125. Why won't Xilinx document their code??
  126. pci-x core
  127. the pacer rep suggested these people as an alternative to exp
  128. Modify Memory after P&R in Xilinx Virtex2
  129. V2P7 Partial reconfiguration, FATAL_ERROR in par
  130. How to generate a CSA tree?
  131. Altera NIOS cyclone edition development board problem
  132. Error message in Mapping while using Xilinx ISE 6.1.03i
  133. Protecting Designs - any suggestions
  134. Altera Cyclone Programming device programming
  135. Altera Cyclone data is incomplete or messy
  136. image file reading in vhdl
  137. image file reading in vhdl
  138. PCB for FG456: layers
  139. Xilinx ISE6.1 Verilog `define macro?
  140. Programming and debugging the Altera Cyclone family
  141. Spartan-3 LC Development Kit from Insight (Memec)
  142. Altera Cyclone Serial Configuration devices.
  143. Dedicated CLK lines in CPLD
  144. What is wrong with my DCM experiment? How come the testbench won't simulate DCM1.
  145. ISE6.1 rom16X1 initialization INIT
  146. FPGA Size
  147. FLASH memory programming with Altera NIOS and same question for Xilinx
  148. Job offer: "Optimization on reconfigurable architectures"
  149. Spartan3 IOB without supply
  150. Newbie Question: No Vsim, Vlib etc in my ModelSim
  151. Anybody know what the REAL story is?
  152. New HDLmaker release available
  153. VSPWorks v4.5.1 (c) Wind River, visualSTATE v5.0.7.88 (C) IAR, LOGICDESIGN AND VERIFICATION V5.1 (c) CADENCE, other ...
  154. Verilog Benchmarks for FPGA research
  155. Large/Fast static RAM
  156. Readbackn on Virtex II Pro devices
  157. Dual Port RAM Block RAM using Core Generaot
  158. Improvement on the modular design methodology...
  159. ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
  160. Local constant (VCC & GND) for partial reconfiguration.
  161. Quantization levels of received symbol for viterbi decoder
  162. min propagation delay in xilinx cpld
  163. submodules with their own constraint files
  164. old articels of this newsgroup
  165. spartan 3 sample
  166. iMPACT error : Done did not go high.
  167. Wierd problem with Xilinx XC9572 ID code
  168. Xilinx ECS - connecting a single net to multiple bus lines?
  169. newbie question: speed grade + area constraint
  170. Tutorials for ISE and Quartus
  171. Synthesis in VHDL vs. Verilog
  172. DPRAM using the CoreGenerator, VHDL-example
  173. plb_sdram, timing error
  174. Xilinx Question
  175. Clock domains
  176. IP or Core
  177. SDRAM Controller timing problem
  178. FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus
  179. Generate the first interrupt for MB XMK
  180. Conversion of NCD files from 5.X to 6.1X, problem.
  181. Where do XPP290 places top-level logic when all three AREA_GROUPs have DISALLOW_BOUNDARY_CROSSING on them?
  182. Virtex and Spartan
  183. AFX BG560 board
  184. Simulating multi-chip design
  185. [newbie] How to get the value of active pins through JTAG
  186. readback spartan2e
  187. How do you initialize signals in VHDL?
  188. VirtexE DLL locked range
  189. Xilinx Virtex II Output Register
  190. Questions about guard bits in CORDIC algorithm
  191. Installation of Xlinx
  192. Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
  193. Winterschool on Embedded Systems (call for participation)
  194. XST cant compile with blaxkboxes.
  195. Where i can get the programming sequence of CoolRunner?
  196. Followup to those that downloaded SeaHDL/SimHDL
  197. fast mod (remainder) algorithm for V2?
  198. Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
  199. v2px70 available?
  200. Altera CPLD - Illegal assignment-global clock
  201. DCM Synthesis - Certify Planner Error
  202. FCCM'04 Reminder -- submission deadline Jan 19
  203. p160 connector
  204. maxplus 2 waveform simulation
  205. how to set the ISP mode for programming CPLD?
  206. Adding internal signals in MODELSIM
  207. How do I make use of local-clocks in a Virtex-2 FPGA?
  208. connecting tristates
  209. Do all the Vertex DCM outs use same global clock tree?
  210. Floating point in Nios SDK
  211. Xilinx Logicore PCI64 Problem
  212. System Ace - Flash card formatting
  213. rs-232 trouble
  214. is this a good idea
  215. Complicated clocking in an FPGA.
  216. HDL Bencher question
  217. C-NIT based complete SoC + FPGAProto preview
  218. Response to [email protected] on high level simulation
  219. please help! state machine
  220. Newbie Question: Compiling VHDL in Mentor Graphics
  221. Partitioning Problem in FPGA and Its Embedded PC Core
  222. help for Viterbi decoder design
  223. Virtex2Pro + SysGen
  224. Getting up-to-date libraries for timing simulation
  225. Question on partial reconfiguration flow...Must use EDIF flow?
  226. Newbie VHDL issue with CPLD
  227. boolean to std_logic
  228. A dilemma: which signal to use as a master?
  229. SOS : 4-bit binary divider circuit PLEASE!!!!!!!
  230. dynamic memory allocation NIOS
  231. FLEXlm reports
  232. virtex-II problems
  233. A difference between VHDL sources working
  234. This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
  235. How to use write flash on board?
  236. Spartan3 prices again...
  237. Xilinx Parallel cable
  238. Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
  239. Virtex-II Pro and DDR2 SDRAM differential IO
  240. [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
  241. Bus delimiter in iseWebPACK 4.2
  242. CHES 2004 - 1st CFP
  243. EDK oddity
  244. FPGA SRAM
  245. Anyone has the AMD flash AM29LV800B verilog model?
  246. LVPECL_33 to LVPECL_25 (virtex-II pro)
  247. Fast Fourirer Using Xilinx ISE
  248. Question regarding the sample design in XAPP290.
  249. How to get first bit '0' position in certain register?
  250. How to get first bit '0' position in certain register?