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  1. Leonardo Spectrum - preserve_signal attribute
  2. Design Verification tools and Resources ?
  3. FFT on Virtex-II (Desperation Imminent)
  4. EDK6.1 vs. EDK3.2 clarification
  5. Using 3.3V compliant FPGA for 5V PCI
  6. FPGA vendors and their patents
  7. ChipScope for ISE 6.1
  8. regarding synchronization
  9. Can FPGA bootstrap itself?
  10. GZIP algorithm in FPGA
  11. 20 surplus XC2V1000-FG456-6C devices available
  12. how to priotize multiple conflicting constraints
  13. GSR in Spartan3 ?
  14. Configuring Multiple V2Pros with Same Bitstream
  15. EDK6.1 vs. EDK3.2 issues
  16. Spartan-2 Bus Macro, which one also?
  17. IOB's
  18. Xilinx Chipscope Sample rate
  19. Polyphase filter
  20. using fpga for sampling audio
  21. Partial Reconfig - PAR fails with ISE 6.1 SP3
  22. Plea for help - 29PL141
  23. Manual Partitioning to Multiple FPGAs
  24. Dual-stack (Forth) processors
  25. confused DCM clkin_period vs true input clock
  26. Xilinx DB-01 info?
  27. 74ls193 in coolrunner
  28. Programming an EPC1 conf.Dev. from Altera
  29. Error in NetGen, "ATAL_ERROR:Anno:Engine.c:476:1.44 - Xdm Exception:"
  30. DCM Jitter?
  31. PREP benchmark
  32. Random logic verilog gate netlist generator
  33. quartussII 3.0 , block editor, how to connect signals of buses
  34. LVDS on Spartan 3
  35. makefile to generate memory contents in Altera SOPC Builder
  36. Xilinx EDK and reference system opb_ssp1_v1_00_a
  37. Use of memory bits in QuartusII
  38. Using DLL "locked" output as a global reset signal ?
  39. APEX fit problem
  40. RFC: ARM+FPGA tiny board
  41. Verilog and VHDL mix
  42. Sensible starter FPGA board
  43. xsa-50 board
  44. Xilinx FPGA Editor - can one see the switch box detail?
  45. 10 GigE demoboards...
  46. Re : fpga +cpu + wireless
  47. EDA tool for testing HDL designs (new update) - www.hightech-td.com
  48. clock
  49. timing constraints and enables
  50. Programmable clock, FPGA PLLs, and Actel PLL Core
  51. Dual 7segment decoder in ABEL
  52. is this enable structure ok for synthesis/high speed?
  53. ISE 6.1.03i Linux...
  54. getting back Xilinx ISE commands
  55. Help: Configure PCI Device in Windows 2k
  56. test
  57. debug sdram application with use of xmdstub (microblaze)
  58. How many PCB layers ?
  59. ASIC FPGA DSP PCB Optics, CMOS, RF, Analog Design jobs @ www.cvpages.com
  60. regarding opto isolators
  61. Sine Wave Generation
  62. Spartan-3 shipping, or perhaps not!
  63. Xilinx Platform Flash Prom
  64. NAND flash interface?
  65. debug application in sdram (microblaze system)
  66. debug with opb mdm for microblaze system
  67. IP suppiler
  68. .mif or .hex memory files?
  69. SPARTAN2 BUFG mapping
  70. Altera EPC16 Configuration Problem
  71. Configuration Altera Decives using EPC16 in PPS mode
  72. Odd behavior of BUFGMUX in Virtex-2...
  73. Building a NN using FPGA
  74. Microblaze uLinux bootloader for SystemACE/CompactFlash
  75. Can Altera NIOS be synthesized on non-cyclone/stratix FPGAs?
  76. Array Divider
  77. Custom Nios Results...
  78. problem with BIG-Numbers?
  79. Very Big numbers
  80. Lattice XPGA
  81. attribute +generate statement
  82. negative hold time
  83. Synchronization of signals
  84. Acquiring a Pilchard or TKDM board
  85. sdram controller problems
  86. power calculation in fpga
  87. Partial reconfig flow
  88. VHDL:Dividing a real number by two??
  89. [Altera/Quartus] Tools to regenerate block schematics from .vhd files
  90. MAC FIR V3.0 POLYPAHSE DECIMATION
  91. Virtex 2 Fastest MUX performance
  92. FIR filter coefficient (with COE file)
  93. [Quartus] File folders changed -> errors
  94. Xilinx training
  95. iteration Vs LUT table entry vs accuracy in Cordic
  96. JAM and Xilinx/Altera CPLDs
  97. Opinion on Altium's nVisage VHDL tools?
  98. mixing LVDS data
  99. New open source utility for using Xilinx Block RAM
  100. 32 Bit APEX optimized RISC
  101. Xilinx webpack
  102. XC2V2000 + System Ace + Reconfig
  103. Xilinx EDK and FSL
  104. Xilinx WARNING:NetListWriters:117
  105. Connecting FPU core on Virtex II Pro
  106. Virtex-3 PRO
  107. Newbie question about VHDL & Xilinx CoolrunnerII kit...
  108. Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
  109. Online debate: Programmable Logic vs ASIC vs Gate Array
  110. ERSA'04, CFP: Extended Deadline: Feb 16, 2004
  111. Rocket I/O receiver
  112. FPGA Database?
  113. Trouble with interrupt controller
  114. need desperate help!
  115. project navigator fails to detect inputs to the module
  116. ASIC FPGA DSP PCB Optics, CMOS, RF, Analog Design Engineering jobs @ www.cvpages.com
  117. ASIC FPGA DSP RF PCB Optics CMOS, Analog Design Engineering jobs @ www.cvpages.com
  118. How may I restrain the P&R to only a small area...
  119. Virtex 2: Partial Bitstream Generation with bitgen -r
  120. Symmetric encryption mechanism in smart cards
  121. Update: Open source ARM, Version 0.4
  122. interfacing Chameleon POD
  123. European supplier of Xilinx chips
  124. A small clock synchronization challenge with Virtex E
  125. Production is line-down, need Virtex-II
  126. Do Xilinx Fix Their Prices?
  127. Looking for *application* development environment w/FPGA
  128. Artificial Intelligence/FPGA
  129. FPGA architecture
  130. Fast Fourier Transform
  131. Modelsim Error Code 211
  132. Abnormal routing behavior for Active Module implementation and bitstream length.
  133. XPART : Will it be released
  134. installing stand alone xilinx impact
  135. Quartus II taking forever to compile
  136. Xilinx ILA -> supported FPGA ?
  137. The fastest interface between FPGA's
  138. Xilinx PAD name to (X,Y) RPM coordinate
  139. I comes up against a STA probem by tool PrimeTime
  140. PS/2 Keyboard opencore (keyboard side) available ???
  141. Dual clock FIFO with Atmel FPGA ??
  142. XPART : Will it be released
  143. CycloneII, NiosII, StratixII more info please....
  144. Reconfiguring at runtime internally?
  145. adaptive viterbi decoder design
  146. Quartus II and Synthesis
  147. Spartan 3 Availability again
  148. Spartan II and 100MHz SBSRAM Interface
  149. Altera Nios UART communication
  150. Sporadic errors in the JTAG chain
  151. Passing user-defined types through the port (global variables??)
  152. how to get a vendor id of a pci
  153. Tools for developing high-speed interfaces
  154. QUES: ODFX/IDFX inferred in syplify, and not in XACT libraries ????
  155. dual port RAM - write cycle problems
  156. 4 bit divisor with flip-flop ?
  157. ByteBlaster fails on Windows 98
  158. Design Flow: PCI or any other high-speed PC interface ?
  159. Altera programming
  160. using IIR in DDC
  161. A problem about GAL26V12
  162. A problem about GAL26V12
  163. Xilinx Virtex II Pro: LVDS_25 vs. BLVDS_25
  164. Is it possible that a Virtex II device performs below its spec?
  165. nios c++ and ethernet [may by ot?]
  166. hold violation cause by crossing clock domain
  167. Comparison of the Co-verification tools for SoC/ASIC
  168. JTAG pin states
  169. binary file to bram tool
  170. Differences between Xilinx ISE and Altera Quartus software
  171. MicroBlaze smallest system implemntation report
  172. Clocking an FPGA??
  173. OS-less first executable how to? Please help!
  174. Syn. warning
  175. Altera DSP builder problem with delay and Integrator
  176. ASMBL
  177. Experiences with Microblaze and Nios
  178. New USB chip for fast FPGA bitstream download
  179. More photos like this..
  180. Manchester II encoder-decoder
  181. asynchronous counter an Xilinx FPGA for a newbie
  182. DLL board level lock feedback
  183. Firewire (IEEE 1394a) link layer IP block?
  184. Phase detector for DLL
  185. One bit Virtex BRAM.
  186. Verilog code to Physical layout?
  187. Where to get FPGA devices for testing?
  188. VirtexII Pro MMU/Cache Setup for VxWorks
  189. Showing design in vpr
  190. V2Pro & PCI Problem?
  191. Is FPGA fully static?
  192. Power extimation?
  193. what is back annotation
  194. pci-x core/ XC2VP/ pin capacitance
  195. FPGA basics
  196. jBits RouteClock
  197. Hot2 configuration
  198. Flip-Chip Package Substrate Solder Issue
  199. Partial Reconfig Spartan 2 - Bus Macros, which one?
  200. FPGA/ASIC design full time job wanted
  201. Asking about FPGA-SPARTAN error in synthizer
  202. ISE6.1 : using virtex 800
  203. modular design routing returns 1 unrouted net GLOBAL_PSEUDO/CLK
  204. building macros for Virtex-II with FPGA editor...
  205. init RAM with .rif
  206. Image sensor?
  207. Which Environment for Xilinx Design?
  208. pjcli commandline tool
  209. Xilinx JTAG download under Linux (urgent)
  210. Interruptions in MicroBlaze
  211. isp Cable for Lattice CPLD
  212. CFP: Evolvable Hardware 2004
  213. Xilinx Decoder Position Open In Metro D.C. (Permanent or Contract, Local or Remote)
  214. bait
  215. TBUF-PAR-Warning in detail
  216. How to do with guard bits practically?
  217. Problem with TBUF-Placing
  218. Wer kennt sich mit Quartus von Altera aus?
  219. FPGA machine-level specification?
  220. How do I fix this type of errors?
  221. Cascading of many stages of DCM...
  222. OT: Flash memory problem on Spirit?
  223. Xilinx DDR Register FDDRRSE
  224. XC6200 bitstream readback
  225. Timing model for MultiTrack interconnects in Stratix?
  226. VHDL newbie
  227. Power Cosumption of a Memory Unit
  228. xilinx EDK and Webpack 6.x
  229. How come NGDBuild derive a clk_36m_tmp/4 clock?
  230. UCF constraints for DCM outputs?
  231. Xilinx Map & Par time spent
  232. software tool kits for openrisc
  233. Altera Active Serial
  234. sccom and win32? when does it come available?
  235. time set up
  236. Quartus doesn't work with Pentium Hypertheading!
  237. Xilinx CoreGen - java - Windows 2000 error
  238. CFP: 2004 MAPLD International Conference
  239. asic vs fpga comparison issues
  240. 10GbE MACs
  241. Xilinx LVDS_25_DT termination issues????
  242. CHES 2004, 2nd CFP
  243. Down Sample, FFT
  244. Synthesizing pipelined multipliers in Synplify Pro
  245. Random data generator...
  246. Lining up data...
  247. error in Quartus
  248. Why is router software not multi-threaded?
  249. systemc download page?
  250. Post-Place & Route simulation with MicroBlaze