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  1. Cyclone and ByteBlasterMV?
  2. XST -read_cores YES doesn't merge the NGC into the compiled file...
  3. EDK 6.2 and Linux
  4. VGA Contoller
  5. Some RocketIOs in V2Pro - Output XXXX
  6. Fast Carry Chains in Xilinx SpartanII FPGA's
  7. XPower: Post-Place and Route Simulation model
  8. XPower: -tb switch
  9. number of BRAMs
  10. Re: AHDL, VERILOG or VHDL??
  11. XIL DCM Reset on XAPP462
  12. Virtex2PV20 programming failed, DONE pin doesn't go HIGH
  13. Problem for DAC/ADC conversion (Stratix EP1S25 Development Board)
  14. Fan Out Problem..
  15. Need help with using inout (bi-dir) in VHDL for Xilinx FPGA
  16. Designing MUX with tri sate bus in xilinx virtex II FPGA
  17. Clock Path Skew in Xilinx Timing Analyzer.
  18. Problem for CNA/CAN conversion
  19. Can I use the Done signal in FPGA to reset my design
  20. Equation to calculate logic required for multipliers
  21. regarding PC to PC schematic transfer incompatibility in Xilinx ECS Editor with Xilinx Project Manager( ISE 5.2i)
  22. VHDL: Use of literal '1' on an input port ?
  23. ATMEL support / Are they serious ?
  24. FPGA pinout
  25. minimum software for virtex II pro
  26. Which HVL is the most popular?
  27. Re: Real-time Image Process on FPGA
  28. Re: AHDL, VERILOG or VHDL??
  29. Xilinx XC9500 CPLD Wired-OR; Wired-ND
  30. Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices...
  31. iMPACT "Programming Failed"
  32. Low cost Improved Parallel Cable 3 PCB + El Cheapo CPLD card
  33. FPGA and CPLD boards
  34. Re: Schematic Edition Tool : Suggestions
  35. Re: study verilog or vhdl?
  36. The Logic Behind License Renewal
  37. SAA7111 YUV
  38. Re: rs232 interface on nios
  39. Re: Metastablility
  40. Logic required for multiplication
  41. Re: Metastablility
  42. FPGA input
  43. vertex II vs Stratix
  44. Verifying multi-cyclicity of multi-cycle paths
  45. vcom in modelsim
  46. signal names in modelsim
  47. Virtex-E, FDRI register
  48. Configuration Bitstream : Virtex-E, FDRI register
  49. Re: XAPP134's VHDL code
  50. ML300 and GigE Experiences
  51. Re: The mapper is getting rid of all my logic!!
  52. Re: Help with Xilinx Ram16X1S example VHDL code
  53. Mapping Logic to Virtex II Block RAM
  54. How do I attach TPSYNC to primitive input?
  55. PCI development kit
  56. PCI development kit
  57. Re: Actel tools (Designer and others) - command line driven compilation?
  58. Re: Spartan-3 Mapping error with ISE 6.1i
  59. Xilinx License Question
  60. Re: AHDL, VERILOG or VHDL??
  61. Can't do a single byte read in Nios?
  62. Re: simulation time
  63. Inserting timing in behavioural simulations
  64. Re: XAPP134's VHDL code
  65. Re: The mapper is getting rid of all my logic!!
  66. How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
  67. Best price per I/O
  68. Re: maybe a stupid question
  69. Re: FPGA Engineer w/clearance - where do you look for a job?
  70. Re: Bus macro in partial reconfiguration
  71. Re: Quartus removes Tristate Buffer
  72. XC18V master parallel configuration
  73. Re: simulation time
  74. newbie - TCP/IP
  75. Re: Athlon FX vs Pentium 4 benchmarks for xilinx's par
  76. Re: Virtex 2 PRO Eval/Development platforms
  77. Re: simalation of gigabit ethernet fails
  78. Re: simulation
  79. Re: Multiple DCM ? (Virtex II)
  80. REGISTER as a COUNTER in hardware
  81. Re: USB Traffic Generation for FPGA Test
  82. Re: Utility for converting .esf file to .tcl file
  83. Msg for Rudolf Usselmann
  84. Replace PPC in V2P with FPGA fabric!
  85. Re: XAPP134's VHDL code
  86. Re: Metastablility
  87. does V2p support tristate
  88. Delay on Virtex-II IOB input FF
  89. Implementing a reliable counter inside SDRAM memory mapped device
  90. Bus interface - read, write signals
  91. licence for Xilinx 2.1i
  92. strange error
  93. Documentation and manuals for Quatus 3.0...
  94. Newbie Question on Xilinx Macros and Pads
  95. Can anyone advise me on how to reduce the compilation time for our design...
  96. Best Starter Guide for Xilinx FPGA Editor?
  97. Can Verilog codes be synthesized with XIlinx XST?
  98. New release TBGenerator (added wave form) - www.hightech-td.com
  99. Release asynchrounous resets synchronously
  100. PWM, PLD programming ,(up/down ramp frequency)
  101. FPGA hangs
  102. Testing a verilog design after synthesis in Xilinx ISE
  103. Software for synthesis
  104. Testing a Verilog design after synthesis in Xilinx ISE
  105. PCB - Mechanical- Embedded design
  106. Modelsim glitches
  107. A newbie question
  108. use of attributes
  109. Why does my RPM creation fail?
  110. Viterbi Decoders with 4x throughput
  111. Spec VPR Results for various processors...
  112. fatal error : help required
  113. Global reset question?
  114. DMA PCI-X core
  115. Xilinx VirtexII Pro downloading with Platform Flash ?
  116. mersenne twister
  117. Module design:why design can't run in "virtex2"
  118. EDK and LMB peripherals...
  119. Anyone else using the USB JTAG board from Mesa Electronics
  120. Xilinx Webpack 6.2 and Verilog `define ?
  121. Jitter in DLLs vs PLLs
  122. Different Finite Field Multipliers!!!
  123. anyone using nios kit APEX?
  124. Design never finish routing?
  125. V2pro + A/D + IrDA + RS232 board???
  126. Looking for a small ARM and/or IA32 based application
  127. Does iseWebPack 6.2w has FPGA-Editor inside?
  128. Any help about this demo board
  129. Dongle compatibility
  130. CpuGen 2.0 released
  131. Xilinx : RLOC ORIGIN
  132. frame length, frame addressing ?
  133. CASCADING DCM
  134. TRST Pin in Altera FPGAs
  135. Mailing list for NIOS kit/Lancelot hackers
  136. Wanted: Insight "Virtual Workbench" for Xilinx XCV300 information
  137. Is WebPACK 6.1 generally broken, and what of 6.2?
  138. XST ff merging - how do I "preserve" flip flops
  139. SRAM Controller Problems
  140. Configuring Altera FLEX10KE using EPC2 device
  141. help needed for NCO code in VHDL
  142. What's the rule of instantiating the global buffer
  143. embedded powerpc in VirtexII-pro
  144. cpu time of the computation
  145. RPM of block RAMs
  146. nios board, apex, tutorial doesn't work
  147. synthesis error - left bound of range doesn't evaluate to a constant
  148. Xilinx iMPACT error: "Done did not go high"
  149. Pbl uploading code on a Spartan II board
  150. netlist tricks
  151. netlist - technology remapping
  152. Active contour model on FPGA
  153. area constrains in UCF (or PACE)
  154. FPGA implementation of ARM and IA32 ISA
  155. Xilinx Spartan 3 configuration
  156. Need to speed up Stratix compiles.
  157. Xilinx ISE Impact crashes during configuration
  158. [Fwd: Re: ngd2edif vs. ngc2edif]
  159. DLL block
  160. Surplus cplds
  161. comp.arch.fpga : Multisource databus
  162. Question: size of Stratix??
  163. DesignCon 2002 Paper
  164. Re: ngd2edif vs. ngc2edif
  165. V2Pro config problems with HSTL_II_DCI pads...
  166. DPRAM issue
  167. Re: ngd2edif vs. ngc2edif
  168. DPRAM design issue
  169. Suggestions
  170. one more inquiry....fpga architecture
  171. Inquiry on configuration file analysis
  172. Suggestions: Eval/Demo Board.
  173. How to work with global clocks and buffers in CPLD?
  174. Done Pin Remains Low after JTAG Configuration of V2Pro
  175. VHDL FSM Problem
  176. Automatic Placement algorithm, help needed
  177. FSM in fpga's
  178. powerpc
  179. ARM+FPGA tiny board
  180. How would you...
  181. difference btw H/W & S/W implementations !!
  182. Modular Design in WebPack
  183. Example using a custom OPB slave core with and interrupt
  184. PC parallel port interface and configuration sources for free
  185. Basic jitter from a CPLD (XC7500XL)
  186. SmartMedia writer (implments using VHDL)....
  187. Xilinx webpack 6.1.03i error
  188. An old FPGA paper back to 1986...
  189. Why warnings: "Input <xyz> never used???"
  190. Warning on DCM min frequency...
  191. Stratix 2 ALUT architecture patented ?
  192. Experience with Simulating RocketIO in Modelsim
  193. Verilog Newbie Question
  194. spying on signals in Quartus (newbie question)
  195. DCM Simulation Error
  196. Spartan 2 XC2S400E and XC2S600E availabillity
  197. JTAG Opcodes for Altera MAX7000S
  198. SRAM bidirectional bus
  199. Re: SHARC 21062/21060 link port implementation on Virtex 2 FPGA
  200. SHARC 21062/21060 link port implementation on Virtex 2 FPGA
  201. ngd2edif vs. ngc2edif
  202. Spartan 3 / XCF02S JTAG problem
  203. Routing algorithm - help needed
  204. CardBus prototype in FPGA
  205. Driving INOUT signals
  206. Fast Single-ended I/O
  207. What is the constraint to define the clock skews in XST?
  208. How to configure FPGA manually ?
  209. ML300 EDK 6.1 Simulations
  210. Why does Xilinx keep saying LVPECL_2.5 and _3.3V are identical?
  211. [Fwd: Solution Update [WAS: Re: EDK6.1 vs. EDK3.2 clarification]]
  212. OpenCore.org DDR SDRAM problems
  213. Usage of Xilinx Library elements in ModelSim simulation
  214. Free PCI-bridge in VHDL for Spartan-IIE
  215. Xilinx Microblaze and C++
  216. Xilinx Microblaze
  217. VQM to EDIF
  218. Inova Semiconductor Gigastar Link between two FPGAs
  219. erasing a MAX device
  220. Barrel shifter synthesis in QuartusII
  221. Help with Xilinx EDK 6.1
  222. ModelSim, Virtex DCM, and clk0 phase problem
  223. Altera ACEX chip wide reset
  224. TCP offload fpga core
  225. Comparator and minimum value address
  226. FPGA info from Embedded World 2004/Nuerrnberg
  227. Lead Free Packages
  228. EDK 6.1 vs 3.2 and OPB Bus resets
  229. old CPLD programmer wanted
  230. multiple clocking in FPGA
  231. Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
  232. Spartan 3 - avaliable in small quantities?
  233. ANN: Graphical Testbench Tool Download
  234. Floating point calculation in Microblaze
  235. Power supply for the Xilinx Virtex Pro FF1152 Proto Board
  236. Copyrights and licenses for NIOS design
  237. altera, xilinx susceptible to power transients?
  238. Amontec problems...
  239. How does ISE6 handle mixed-edge design?
  240. Is this a bug in MAP?
  241. why ISE par does not tell me all buffer usage?
  242. Multiple PicoBlaze/Bus access
  243. Is there an easy way to get a list of unused pin in ML300?
  244. Virtex-II Speed grade -6 exist?
  245. Open Source Arm core version_0.5
  246. Microblaze instruction timings
  247. Unix workstation runs ISE 6.1 slower than a PC?
  248. Simulation MODEL for SRAM
  249. Xilinx ISE 4.2 Unisim Block RAM bug?
  250. Source code for NIOS GNU toolchain