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  1. scatter gather DMA in OPB MAC core
  2. Programming FPGA in Xilinx Virtex 2 pro board
  3. Virtex II : partial reconf, bus macro
  4. CPLD mistery. Help.
  5. Nios II and eCos
  6. Re: TCP/IP in Virtex II Pro
  7. Linux on Xilinx v2pro: OCM access?
  8. IOBs in NGC - problem with OBUFT
  9. compressing Xilinx bitstreams
  10. Xilinx XST synthesis removes input pin even though it's LOCed
  11. SPARTAN-IIE -> LVCMOS18
  12. How to create an EDIF file from ISE Foundation?
  13. VHDL code for EPP parallel port with xc2s200-pq208
  14. Dilema 2731
  15. Quartus II - Disabling the Optimizer to use gate delay
  16. Altera unable to respond
  17. Is there a verilog version of PicoBlaze?
  18. Synplify_pro
  19. If you need higher fmax for your FPGA design
  20. Xilinx RAM64x1D simulation problems
  21. help for finding a company which can provide FPGA based PCI board with ethernet port
  22. Het zal toch niet zijn wie ik denk dat het is?
  23. Many UARTs on Avalon bus with NIOS cpu
  24. Config solution between
  25. XCS10-84PC: How JTAG-Pins as I/O ?
  26. example for excalibur epxa1
  27. Example for Excalibur EXPA1
  28. Example for Excalibur EXPA1
  29. Example for Excalibur EXPA1
  30. Suse 9.1 Linux and Xilinx ISE 6.2i
  31. MGT pin details(Xilinx Virtex 2 PRO)
  32. C Header files for User Design Logic in the Nios.
  33. importing a design from maxplus2 to quartus II ver 3
  34. length of parallel cable attached to P IV xilinx jtag cable
  35. Progress in FPGA static Icc timeline degrade
  36. Arjen Jongeling, een oude bekende
  37. Using Altera libraries for Nios Dev Board
  38. pulse generation using SRL16E on a Virtex-II
  39. how to connect my IP-Core to Microblaze in EDK and ISE with IPIF
  40. Starter Kit for Linux in Virtex?
  41. Library Mapping
  42. Altera CLKLK_FB use when OPERATION_MODE=NORMAL
  43. Content of RAM
  44. >Math Skills = >Engineer ?
  45. Atmel WinCupl
  46. Stratix DSP Block: Choosing which FFs are enabled
  47. FPGA serial programming troubles. (Virtex II)
  48. 90nm Xilinx FPGA?
  49. Free Seminar
  50. Several Problems with Spartan2 Configuration
  51. Design Compiler, how do I use a derating library...
  52. Indepedent Stocking Distributor of Electronic Component Spare Parts
  53. Xilinx .bit to .svf...
  54. a newbie question
  55. RAM in Altera EABs and Xilinx Block Rams
  56. Megawizard Plugin and SDRAM controller
  57. Costs of IPs
  58. Low Power FPGA Design Seminar
  59. Xilinx ParallelCable IV vs. Linux
  60. Xilinx System Generator problem: ERROR:NgdBuild:604
  61. Microblaze asm and C shared variables
  62. Problems about Using Xilinx Command Line !
  63. Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
  64. Xilinx Coregen
  65. Xilinx: infering dual port ROM in VHDL
  66. example designs for Xilinx System Generator ?
  67. Xilinx Floorplanner
  68. Avoid action on very short peak on input signal (Xilinx Spartan 2)
  69. run-time management of logic resources
  70. How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
  71. Cores into fpga
  72. Reading Back Configuration of Slice/LUT
  73. Virtex4: I don't understand their thinking....
  74. Frequency synthesizer.
  75. can't trap custom ITon NIOS
  76. Help For Linux ISE users (DLC5, impact)
  77. Virtex-4 suggestion: TSMCCCS change
  78. delayed clocks on timesim simulation?
  79. Stupid Xilinx Rubbish
  80. Is Virtex-4 LX succesor for Spatan-3?
  81. Xilinx Co-Founder Bernard 'Bernie' Vonderschmitt Passes Away
  82. LPM Megafunction : LPM_SHIFTREG timing
  83. Xilinx 6.2 - - WARNING:NetListWriters:303
  84. Digital Clock Manager (DCM) Question
  85. Altera Instructor-led course on Designing with NIOS II
  86. lancelot VGA daughter board for altera nios dev board
  87. Question about Xilinx packages and CLB ordering
  88. xilinx gigabit MAC core full vs half duplex
  89. handel-c library file
  90. handel-c library file
  91. Where is my Digital Up Convertor in Logicore ??!!
  92. V4 teaser
  93. slice # change from .syr to map report
  94. Nios II really available ?
  95. IR_CAPTURE fail on Virtex2
  96. Virtex-4 availability?
  97. SOPC BUILDER - SOFTWARE GENERATION
  98. Hardware implementation of the Xilinx configuration CRC generator
  99. Virtex-4 FX transceiver jitter
  100. DCM in Xilinx
  101. ISE 4.2i Impact and Windows XP not working
  102. Good SDRAM Controller
  103. Problem with the "Write RPM to UCF" command (floorplanner 6)
  104. comp.arch.fpga: reset strategy
  105. Rocket IO : Sensitivity to RefClk Phase
  106. Rocket IO Timing Problem : sometimes miss Half Word
  107. CFP: Workshop on Application Specific Processors (WASP 2004)
  108. Where is my Digital Up Convertor in Logicore ??!! :)
  109. Variable Frequency and Voltage Supply
  110. Quick question
  111. parameter feature of AHDL in Xilinx
  112. Book on SPARK: parallelizing high-level synthesis tool
  113. IDE/ATA _device_ core availablility
  114. PAR runtime error
  115. where is ISE 6.2 SP#3 ?
  116. USB OTG high speed
  117. Virtex-II Pro slave serial configuration problem....
  118. Partial Reconfiguration clock enable problem
  119. Three-phase PWM generator in VHDL
  120. FPPTA?
  121. MAPLD 2004: Registration Open and Program Announced
  122. 5 V inputs to 3.3 V CPLD
  123. FPGA + A/D converter
  124. How can I get an output clock phased align with the input clock.
  125. tri-state in altera
  126. Problems with PLAmap (part of RASP package) from UCLA
  127. Seven leading PC processors benchmarked on Quartus-II Web Ed place&route
  128. NIOS I memory usage
  129. converting design from ise 6.1 to 6.2 problems
  130. Problem with carry reusing RPM with ISE 6.2i and VirtexE
  131. NIOS 2 memory limitations
  132. Problem with carry reusing RPM with ISE 6.2i and VirtexE
  133. Testing a lot of FPGA
  134. Configration............problem..............
  135. Is this a bug in ISE 6.1?
  136. solderless breadboard + fpga + smt-adaptable socket?
  137. Serial I/O Standards
  138. SALE notebook parts
  139. EDK 6.1
  140. VHDL warning " Feedback mux " from synplify pro ...thx
  141. VHDL test bench in Quartus
  142. how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
  143. Xilinx System Generator
  144. Yawn...Cannot copy Acrobat Reader -write_timing_constraints YES directly into .xst file...
  145. how can I merge 66mhz pci clock to 33mhz clock?
  146. Tool to help detecting race conditions with asych inputs?
  147. Sr. Design Engineering Opportunities
  148. Job Opening - Product Planning Manager
  149. Propogation delays and setup times
  150. ise 6.2 lvdci_33
  151. Good Devlopement Board for learning
  152. LEAD HARDWARE ENGINEER - Santa Barbara
  153. SystemC book
  154. SDRAM controller
  155. Xilinx mb-gcc, linker scripts and splitting Object-file sections
  156. SDRAM
  157. Creating Orcad symbol for FPGA with large pin counts
  158. Readback on Vritex2, help me.
  159. How to generate a 320x200 VGA signal?
  160. CPLD Board design newbie questions
  161. ise 6.2 + linuxdrivers.tar.gz + kernel 2.6
  162. Read/Write data from/to SRAM
  163. www.opencores.org ???
  164. AWGN
  165. Virtex2P co-simulation problems using Modelsim and smartmodel
  166. VPR & Reconfigurable system ?
  167. What can I do if my chip can't meet timing?
  168. test
  169. Driving fpga pin out over long cable
  170. HSTL and Virtex 2
  171. Nios II = Microblaze
  172. NGDBUILD warnings...please help
  173. I have problem with readback for virtex2
  174. How to convert a pattern to SVF
  175. VHDL simple question: is 2-D array synthesizable
  176. HOWTO calculate the binary size of a .hexout/.flash/.germs file
  177. spartan 2 demo example
  178. strange behaviour of the design
  179. is RAMbus going to resurect itself as another DDR2 format?
  180. Altium FPGA board
  181. Reg learning FPGA backend
  182. More fun with VHDL
  183. OT: Electronics learner kit?
  184. FPGA Board with Flash Memory
  185. USB HUB?
  186. Old XCV50 FPGA and Ethernet
  187. Seeking Chameleon Systems white paper
  188. DS-BD-V2M1000 datasheets?
  189. How to handle different proccessing speeds?
  190. XIlinx V2P7: DCM won't lock
  191. Xilinx hypertransport lite reference design.
  192. IT careers
  193. FREQUENCY DOUBOULER BY MAX PLUS......
  194. shift register by block RAM
  195. Altera LP4 Need Help With Device Drivers and Setting Up
  196. Trying to build simple demo using XPS and XC2VP20
  197. Timing Questions?
  198. Debugging - Post-synthesis simulation
  199. Xilinx EDK (PPC): Problems Porting to Memec 2VP4LC Board
  200. Chipscope with clock enable.
  201. I2C Slave
  202. C-code to control FPGA with Leon
  203. Xilinx V2P: DCM and changing input clock
  204. Initialize Blockram from file
  205. Inversion of signals on synthesis
  206. Nios II Going Live...
  207. opb_gpio with interrupt- v2pro
  208. NIOS Board Stratix Edition - FPGA won't configure
  209. Webpack 6.1, ISEexamples, and CoreGen
  210. How to select an FPGA size (beginner)
  211. Meaning of output value?
  212. clock buffer in Leonardo Spectrum
  213. 64B/66B at sub 10Gbps in Xilinx MGT
  214. Malfunctioning dual port block ram.
  215. Drive strength on I/O pads
  216. Micro : Bus
  217. Quality of timing simulation
  218. Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give me a hint?
  219. How do I perform RTL simulation with a Core Generator RAM and multiplier?
  220. DLL - Change in input frequency (CLKIN)
  221. Atmel Zigbee solutions
  222. IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
  223. question about filter design vhdl
  224. Xilinx training
  225. Clock Generation from Asynchronous Data Stream
  226. How to replace Triscend - Xilinx plans for the future
  227. Re: FPGA vs Microprocessor: newbie question
  228. Xilinx Foundation [*.SCH -> *.VHD]
  229. Low cost FPGA dev board with high speed i/f?
  230. Phase alignment
  231. load on a clock signal in FPGA
  232. std_logic_vector vs unsigned
  233. Please, I need help with a mpeg layer 1 decoder in vhdl
  234. Phase relationship management
  235. drive multiple outputs with the same value on EPM3064?
  236. Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
  237. FPGA Timing question
  238. EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
  239. MCNC benchmarks (was: Simple way to generate random netlists of ALUcells)
  240. Quartus Internal Errors
  241. 5V signals at Spartan-IIE inputs
  242. Clueless newbie question -- what has changed to make moisture suchan issue?
  243. best fpga development board?
  244. Quartus II Web Edition
  245. Simple way to generate random netlists of ALU cells
  246. Using a FDDRCPE primitive. VIRTEX-II
  247. Updating a XILINX Project
  248. EPCS4 Configuration+firmware, Quartus problem
  249. Anyone who has worked with Altera Cyclone???
  250. ISE 6.2i Synopsys Design Compiler libraries?