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  1. PCI Core implementation in Spartan 2E FG456 package
  2. XILINX RocketIO / MGT signal quality problems
  3. Xilinx registers resetr value
  4. How to program a spartan-3
  5. Converting High Rise Time clock to Low Rise time clock - Chellenge!
  6. Looking for ways to keep diagnostic signal from being optimized out (Xilinx)
  7. Sydney-X1 FPGA Computer, US$499 introductory price
  8. Resources on FPGA wanted...
  9. Altera Cyclone Web presentation
  10. Xilinx clock net skew vs. MAXSKEW
  11. FPGA Selection--
  12. Cheap FPGA's
  13. Changing directory name in Quartus
  14. xilinx ngdbuild old command flow problem
  15. Area constraint on a sub-module
  16. Altera FPGA's
  17. Altera DEMUX Megafunction - does it exist ?
  18. Open Collector Circuit - How to Simulate?
  19. 32-channel PC-based logic analyzers
  20. Xilinx XC9500 CPLD internal pull-up??
  21. Boards Comparable to Alpha-Data's ADM-XRC-II
  22. Xilinx FPGA Die Size
  23. IDE or ATA controler on a Fpga
  24. Using Verilog to embed the synthesis date and time
  25. PLL phase after compensation
  26. fpga board with audio in/out (xilinx fpga) ?
  27. Warning During Simulation
  28. Altera Avalon Bus Signal Monitoring?
  29. Memory width on Spartan-3 boards
  30. Xilinx 6.2i ISE WebPACK running under wine?
  31. Problem with LogicLock and register packing
  32. FPGA Development board with onboard Ethernet PHY
  33. ICM'2004 : Second Call For Papers
  34. FPGA in a Compact Flash format.
  35. fpga low cost and available
  36. XILINX
  37. buy xilinx, altera, lattice, and several other devices below market costs
  38. BUY FPGAs and OTHER COMPONENTS BELOW MARKET PRICE
  39. ChipScope Pro : Stimulation
  40. OPB_HWICAP clock
  41. FAE Job opening
  42. How to refresh pins in Xilinx PACE
  43. How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
  44. twos to ones and ones to twos compliments
  45. SPARTAN-3 RDS resistor
  46. Network Communication Using Nios Daughter Board
  47. WISHBONE read cycle VHDL implementation
  48. News, Sydney-X1 FPGA Computer Challenges Commodore, Amiga and Apple
  49. Altera FIR compiler 3.1.0, no filter ouput
  50. RE: Xilinx Virtex-II Configuration in Slave Serial
  51. Spartan3 Dev Boards
  52. MUXCY-based multiplexers
  53. Xilinx EDK PCI
  54. Clock generation
  55. Nios reset behavior
  56. connecting a fifo to avalon bus
  57. programmable voltage control of a VCCIO Bank
  58. How to deal with unrouted nets in a partial reconfigurable assembly?
  59. Enum type as array range
  60. extending a signal pulse
  61. Nios SDK - understanding nm output
  62. Xilinx Virtex-II Configuration in Slave Serial
  63. High Temperature FPGAs
  64. Quartus SOPC Builder doesnt Recgnize my .elf file
  65. Re: extending a signal pulse
  66. mcu vs fpga help me to choose !!
  67. WinCUPL state machine for 16V8
  68. synchronus reset on bufg? (xilinx)
  69. micron sdram module
  70. Xilinx Virtex 4
  71. Altera SOPC SDRAM & CLK Input?
  72. Hazard Analysis ???
  73. Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif
  74. KCPSM3+vhdl+verilog
  75. MicroBlaze in Spartan3, external memory interface
  76. dots during P&R, ISE
  77. speed in FPGA
  78. Available: Open Source VHDL parser - for free
  79. Xilinx PAR guide files
  80. NIOS 2 HAL, libraries, ...
  81. Re: Is the Xilinix XC3020 atill supported?
  82. Using gprof with Nios II
  83. Programable Logic & Video stuff
  84. Ethernet packet..
  85. Same bitstream files give different behavior.
  86. FIR filter running out of FPGA memory in stratix ep1s60
  87. Altium CircuitStudio 2004 vs for FPGA support
  88. Xact 4.1.2
  89. Xact 4.12 or 5.0
  90. FPGA to PCI Bus Interface
  91. RC100 Video DAC
  92. Xilinx Student Edition 4.2i
  93. Modelsim crash (code 211) when using library
  94. Need some help regarding dynamic reconfiguring of the pin connections
  95. Altera configuration Problem?? Help
  96. C16 processor from Opencores.org
  97. Xilinx Virtex II - questions about CLOCKGEN module for EDK (Multimedia Development Board)
  98. PCI Timings
  99. Nios2 on Parallax Cyclone board (SmartPack)
  100. Do i need to use DCM ?
  101. Xilinx Place and Route with changing LUT values
  102. xilinx spartan 3 $99 board...help
  103. Xilinx bitstream AutoCRC algorithm
  104. Info on FPGA routing algorithms?
  105. Spartan 3 termination question (DCI)
  106. Pre-PhD fellowship
  107. Virtex II Pro - Frame Addressing
  108. Icarus Verilog for Windows
  109. comparison between FPGA and computer
  110. configuration for a mixed mode VHDL-verilog lang
  111. EDA apps on Mac OSX?
  112. Xilinx Student Foundation Edition on Windows-XP ??
  113. programming to simulatin
  114. programming to simulatin
  115. extending a signal pulse
  116. runing a bootloader on a Virtex II Pro Board???
  117. How to constrain a divide by 3 clock?
  118. Nios - Ethernet Frame Format
  119. Nios - Ethernet Frame Format
  120. false paths, Synplify
  121. Chipscope inserter changes net names.
  122. RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
  123. FSM in illegal state
  124. Are IO buffers required?
  125. Urgent : Xilinx PACE question
  126. Synthesis failure Xilinx WebPack XST
  127. Minford Altera FPGA CPLD Byteblaster Downloader
  128. Re: Why 18X18 Multipliers in Altera and Xilinx?
  129. RAMB16_Sx instantiation template
  130. Difficulty in routing sinita/sinitb in block RAMs...
  131. Understanding Xilinx Spartan 3 datasheet IOB timing information
  132. Re: new Lattice FPGAs vs Cyclone and SpartanIII
  133. spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
  134. Applicability of mult_style in XST.
  135. Universal IC programmers -----> Distributor wanted
  136. BRAM problems using JBits
  137. Place & route question in Xilinx...
  138. Xilinx FPGA routing question
  139. Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
  140. Puzzled Simulating with 'X' input Quartus II v4.0 sp1
  141. ISE
  142. Compensated clock in Stratix
  143. FPGA/ASIC design comparaison
  144. [Xilinx 2VP] DDR + Differential Input
  145. Re: PCI-X DMA problem w/ Xeon?
  146. seperate fpga programm and a table in altera
  147. CfP - Track on EMBEDDED SYSTEMS at ACM SAC 2005
  148. NIOS generated code
  149. Why 18X18 Multipliers in Altera and Xilinx?
  150. crc32 vhdl implementation (4 bit data)
  151. uClinux on MicroBlaze
  152. MAP: what are route-through look up tables
  153. FPGAs starting with incorrect bitstream !?
  154. Multi-phase Motor Controller?
  155. A simple VHDL question
  156. A simple VHDL question
  157. A simple VHDL question
  158. VHDL in Xilinx : why this signal is regarded as Global Clock ?
  159. FPGA SDRAM prototyping
  160. new Lattice FPGAs vs Cyclone and SpartanIII
  161. Re: Xilinx VS. Lattice ABEL code a standard?
  162. nios-run ignores kbd.
  163. Why this statement renders TWO multipliers in XST?
  164. Compile 30% of my multipliers with LUT?
  165. Does Xilinx have the worst web site on the planet?
  166. reduced power Xilinx® Spartan-3(TM) FPGAs
  167. DCM ISE6.2.3 sim problem
  168. How to prevent MAP from removing floating inputs?
  169. Compilation relation between `ifdef and //synthesis translate_off
  170. Compact FPGA Board?
  171. Quartus web editions vs licenced compatibility problems
  172. *RANT* Ridiculous EDA software "user license agreements"?
  173. Cyclone 5V Tolerance
  174. GAL22V10D vs GAL22V10A
  175. Xilinx $99 Spartan-3 kit
  176. FPGA with fully asynchronous RAM
  177. PCI-X DMA problem w/ Xeon?
  178. Problems with custom IP in Xilinx Project Navigator
  179. a question in the pci interface design
  180. Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
  181. Trouble with $readmemh in ModelSim
  182. Altera SOPC Master Peripheral Design?
  183. ANN: Xilinx Delivers Lowest Cost, Easy-to-use $99 Spartan-3 FPGA Starter Kit
  184. File format *.eqn in Altera IDE
  185. Where are the EDK3.x service packs?
  186. Programming Nios Ethernet Development Kit
  187. Answer Record # 18857 compiling modelsim library
  188. Download Nios II evaluation version today
  189. FPGA jobs in Germany
  190. Battle of the Vapours
  191. Programming Altera Devices
  192. GT10_PCI_EXPRESS_n
  193. XILINX GMAC Core 4.0 - HALF Duplex
  194. XILINX GMAC Core 4.0
  195. How to add clock delay in CPLD?
  196. Running precision on Mandrake 10
  197. clk inputs, are they all same?
  198. PROTEL DXP 2004 / NANOBOARD / 3rd Part board
  199. Spartan 2
  200. Short Course by Dr. Abbes Amira:Accelerating Matrix Algorithms on Reconfigurable Hardware for Image and Signal Processing Applications
  201. How to Connect User-Defined Master Peripheral to SDRAM Slave Peripheral in SOPC Builder
  202. Simulation Tool with Video Display
  203. simprim X_FF component
  204. Nios stops responding to interrupts
  205. GCK0 Problem
  206. Xilinx ML310 Experience?
  207. Newbie question -fanout of iopins in fpga
  208. RocketIO transmission error
  209. Post-Map Simulation
  210. Using a BlockRam in an async FIFO for bus width conversion ?
  211. Large fast FIFO?
  212. open source FPGA tools
  213. Forget the RAMs, I can't get Quartus to use the cascade chains!
  214. CFP - WASP 2004 - Abstracts due July 1
  215. Why does Quartus take 4 hours for a pin I/O change?
  216. Looking for Fax software
  217. Xilinx's interp on EDIF properties
  218. synchronizer and Reset question?
  219. Divided by 11 in VHDL
  220. DPLL in CPLD
  221. booting fpga and xscale
  222. Re: Exponential Function
  223. Readback Problems
  224. Xilinx Sparta-3 configuration
  225. -mapstyle option in BATCH mode operation of XST
  226. -mapstyle option in BATCH mode operation of XST
  227. Communication FPGA & MII
  228. 5V board in a 3.3V PCI slot
  229. Problems with a Virtex-II Engineering Sample
  230. Division in Xilinx
  231. EDK 6.2 ISE verilog toplevel possible ?
  232. Asteroids Deluxe in an FPGA
  233. ANN: Low cost & high speed JTAG interface
  234. Re: Is the Xilinix XC3020 atill supported?
  235. Trying to remember how to use Quartus
  236. Re: New: read/write to D2SB fpga
  237. Re: Initializing data in EAB ram
  238. Newbie Q
  239. Re: Altera Quartus II on Linux
  240. Re: Unused signals in Modelsim
  241. VIRTEX v Spartan 3
  242. ROM instantiation question
  243. Re: JTAG - XC2S200E-PQ208
  244. Re: Spartan/SpartanXL Device Selection
  245. Re: system verilog
  246. Re: Synthesis of loops
  247. Re: Linux.
  248. Re: Unused signals in Modelsim
  249. Re: JTAG - XC2S200E-PQ208
  250. Newbie: Spartan XCS10