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  1. DSP/FPGA/video board?
  2. IP Coregen: FFT v2.1 IP core regd.
  3. Ethernet
  4. SSO and decoupling relationship
  5. Xilinx - Proper VHDL for Bidirectional Pins
  6. Xilinx Swift interface Licence (?) problem
  7. plb_ddr_1.00.c cas latency ?
  8. XC2V250 protoboard
  9. Floorplanning funnies
  10. XST synthesis
  11. Meaning of _PINMAP in XDL file
  12. Virtex II LVDS plus DDR?
  13. Quartus II v4.1 for PCs (-) Altera - new !
  14. How to make ByteBlaster II
  15. FPGA SPARTAN 2 BOARD SCHEMATIC protel
  16. Help, synthesis for Spartan XL; does FPGA Express licenses for ISE3 or 4 expire?
  17. GAL,PAL,PLD, CPLD,FPGA
  18. Microblaze Cache
  19. NIOS II Sim
  20. XST: init inferred block RAM. Possible now?
  21. Quartus, building "Safe" FMSs
  22. Edk BMM file problem in ISE
  23. A timer with Celoxica RC100
  24. [Synthesis][VHDL] HowTo prevent Removal of Registers ...
  25. xilinx ultracontroller reseting in simulation
  26. Free Flash PROM programming tool for GNU/Liunx
  27. Viewing internal nets during Quartus functional simulation
  28. CFP: International Workshop on Applied Reconfigurable Computing (ARC 2005)
  29. Verilog ASIC conversion to Xilinx FPGA - GOTCHA
  30. anybody ported Jrunner to NIOS I/II??
  31. Porting design constraints from A to X: help
  32. Announcing JOLT - Yet Another Xilinx Programming Tool
  33. Nios II debugging with gdb
  34. Xilinx Spartan3 DCM Procedure
  35. Regarding BIST in FPGA
  36. nand flash memory chips
  37. Re: Spooling from FPGA to the PC
  38. V2PRo: Rocket IO Question
  39. Xilinx Spartan 3 XAPP462 DCM (Digital Clock Manager)
  40. PacoBlaze
  41. linux on virtex 2 pro board
  42. Secret to SignalTapII Incremental Build?....
  43. Rocket IO Deserializer
  44. XC3S50 DCI Application
  45. XC3S50 DCI Application
  46. 3S50 DCI Application
  47. Q: DCI used as current limiters?
  48. embedded PCI
  49. Xilinx WebPack Spartan3 DCM implementation problem
  50. IEEE ICM'2004 Extended Call For Papers
  51. New cache
  52. How to download USENET News **in-spite** of firewall blocks
  53. where to post job in china
  54. Spooling from FPGA to the PC
  55. JTAG Vcc pin on coolrunner
  56. Xilinx VQ100 package drawings?
  57. Spartan 3 Xilinx IO Standards
  58. Usercode in bit/mcs file
  59. Minford MF160 FPGA and CPLD Downloader -- Replace for Altera ByteBlaster II
  60. NIOS II memory devices on tristate bridges
  61. Re: LEGO mindstroms and FPGA
  62. SSO and other banks behavior of Xilinx FPGAs
  63. SDRAM Controller on a cyclone dev kit
  64. Hardware/Software Communication in Virtex-2p
  65. Spartan 2E problem
  66. Minford MF160 FPGA and CPLD Downloader -- Replace for Altera ByteBlaster II
  67. clock enable multicycle doesn't work with altera altshift_taps megafunction
  68. Free Spartan3 download program for GNU/Linux
  69. is it possible to time optimize combinational logic ..LeonardoSpectrum.
  70. FIFO on Spartan 2E question....
  71. NIOS II - Instantiating array on SDRAM
  72. [CPLD] Novice
  73. Xilinx 804 Aurora vhdl Design patch
  74. Infiniband
  75. We can supply obsolete Xilinx parts
  76. Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)
  77. Using SDRAM on Xilinx AFX V2P board
  78. Do you know how to reconfig the DFS of Spartan DCM at runtime
  79. What schematic tool (VHDL) is the best?
  80. What is the multicycle path? (LeonardoSpectrum - Time Analysis)
  81. Test 1,2 Test 1,2
  82. NIOS SDRAM controller simulation
  83. Minford MF160 FPGA and CPLD Downloader -- Replace for Altera ByteBlaster II
  84. Xilinx POD internal circuit diagram
  85. vertex-II configuration architecture
  86. Quartus warning
  87. Dual Microblaze System
  88. Can PPC in V2P reconfig the FPGA slices?
  89. Problem instantiating xilinx blockram ramb4_s1_s16
  90. FPGA programming issue with Xilinx POD and PROM
  91. xilinx Synthesis report - please help..
  92. 95108 doesnt program
  93. IEDCS'04 Design Contest
  94. Looking for suggestions/recommendations on 64-bit Linux machine
  95. Different capabilities
  96. How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
  97. CLOCK_SIGNAL Constraint.
  98. How big is LEON on Virtex2?
  99. get net name after place and route, ISE
  100. Request for 28 BIT ADDER maximum clock rates for Vertex II FPGAs
  101. new XILINX 9500XL datasheets
  102. ADV: 2M Gate FPGA Protosystem (DIY - selfmade) for sale (0.99 starting no reserve)
  103. DDR Lines on FPGA : Physical considerations
  104. Primitve 3D Graphics Library
  105. scheduling in run-time reconfiguration
  106. xilinx SW state machines enumeration
  107. FPGA/CPLD from logic diagram?
  108. Automated Macro Grid to RPM Grid?
  109. SelectMAP problem
  110. ISE 6.2 : Place problem with V2PRO
  111. How crate symbol from VHD?
  112. Hardware Multipliers with Virtex II
  113. Xilinx PowerPC simulation problems
  114. why?
  115. Understanding Xilinx Timing Constraints Analysis Report
  116. Example of network router and # of LUTs utilized - Searching for 3rd party compilation of "typical" specs
  117. Spartan 3 Starter Kit VHDL 7 segment LED driver
  118. Spartan III I/O robustness
  119. let me have logic design for traffic light
  120. Help wanted for ethernet on xilinx fpga Virtex2 multimedia demonstration board
  121. XC4010E/XC2V1000 problem
  122. Sync data between two clock domains
  123. Newbie Xilinx Question: How to keep past designs?
  124. Differences between FPGA & CPLD
  125. Altera winner?
  126. How important are software tools while choosing FPGA
  127. Board suggestions
  128. Carbon nanotubes
  129. Now I am really confused!
  130. nallatech ?
  131. Spartan Software
  132. synchronous FSM
  133. Impact running on wine?
  134. Impact running on wine?
  135. propagation delay
  136. Newbie Question: Unused pins in the constraint file
  137. RocketIO in full bypass mode
  138. Xilinx Student Edition 6.x?
  139. Mars Rover Glitch in "Gate Array".
  140. ABEL support for legacy chips
  141. LEGO mindstorms and FPGA
  142. Synchronizing Reset De-assertion
  143. xilinx edk6.2.03i simulation with ncsim
  144. Error Using Block Ram in model sim XE 5.7
  145. Error Using Block Ram in Model Sim XE 5.7
  146. Newbie Question Clocks on the Spartan 3
  147. Microblaze opb_emc
  148. Power Supply for Xilinx FPGA
  149. Acceleration
  150. CAN Controller
  151. Re: EDK tutorial?????
  152. Comparing Quality of Results of FPGA CAD Tools
  153. EDK tutorial?????
  154. Reconfigurable system
  155. What is the future of superconducting circuits
  156. Microblaze / XMD question
  157. NIOS Gnu Tools and Dynamic Memory
  158. What is the price of the micro-blaze, ... ?
  159. Using ISE flow in EPS
  160. Call for Participation: 2004 Workshop on Application Specific Processors
  161. i2c controller and Linux driver
  162. Verilog to VHDL conversion
  163. xilinx: non LOC pins causing havoc
  164. Virtex 2 Pro OCM question
  165. practical Virtex2 output buffer speeds
  166. Manipulation on netlist for faster simulation.
  167. Re: Guidelines for Timing Closure on FPGAs
  168. Guidelines for Timing Closure on FPGAs
  169. Need StateCAD 4.11!
  170. Matlab/Simulink - System Generator HDL Co-Simulation
  171. nco and phase detector
  172. Can I use RocketIO to generate pulse edge with very high precision?
  173. PCI express FPGA board
  174. clock synthesis with RocketIO
  175. Xilinx Spartan-3 Supply Issues?
  176. FPGA and RS422
  177. Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
  178. Spartan 3 errata and pricing
  179. ISE WebPack and IPs (no CoreGen)Xilinx
  180. Instantiation of BUFGMUX
  181. Re: ChipScope Pro Loading Memory
  182. VGA Signals
  183. SPARTAN-3 VCCAUX supply current
  184. Clock generator
  185. Best tool(s) for filter float->fixed->VHDL flow?
  186. Any advice on programming XSA-50 w/ programming header pins
  187. adding real UART to xilinx ultracontroller design.
  188. ChipScope Pro Loading Memory
  189. Pointer to a good article on clock domain crossing
  190. Fast Memories
  191. SPARTANII pinout table mysteries ???
  192. DDR or SDR ? Memory controller in FPGA
  193. Spartan 3 prices
  194. Downloading program to Nios
  195. Virtual Computer Corporation (VCC) Virtual Workbench VW300
  196. LE and EAB on FPGA board
  197. FPGA prototype board with ethernet interfaces
  198. How much salary for RTL design engineer in Toronto Canada?
  199. Openings in ASIC_Embedded In World' Top 3 Chip Company_Bangalore_India
  200. Xilinx is still in YEAR 2003 ?
  201. Altera Configuration Device
  202. Fpga eval. board with spdif receiver?
  203. Active modular implementation of modules created with the generate statement
  204. [VHDL] Personnal type as port
  205. Altera Bidi ports, Tristate Buffers & Prop. Delay?
  206. What has happened to www.free-ip.com?
  207. uLinux for Memec-Insight VP20 board ?
  208. Static Timing Analysis
  209. Foundation evaluation on linux
  210. NCD difference
  211. Suggestions for programming flash RAM for SoC via FPGA
  212. fpga vs. cpld
  213. Disable CDR in MGT
  214. RPD File Format ?
  215. Call for Papers: ASYNC-2005 (New York City)
  216. pci X open core
  217. Problems with device
  218. Implementing control registers (VHDL)
  219. XST vhdl adder with carry out : broken carry chain
  220. wishbone protocol documentation
  221. connecting entities
  222. connecting entities
  223. RISCWatch w/ Linux running on ppc405D: Virtual/Physical mem issues
  224. Spartan 2E FG456 package file
  225. FPGA vs CPLD
  226. Choosing PLL
  227. I need a cheap PC/104 FPGA module
  228. Dcm clock for fpga
  229. VHDL file equation
  230. vhdl code : altera vs xilinx
  231. XST Disabling warning 524 (Removal of unconnected blocks)
  232. On-Chip Oscillator
  233. ramdon noise generation
  234. PCI driver for ARM processor
  235. How to set Microblaze frequence?
  236. configuration SRAM cells in Xilinx/Altera FPGAs
  237. www.opencores.org?
  238. Programming a LCD display with a Celoxica RC100
  239. CALL FOR PAPERS. Special Issue: Operational Control of Wafer Production. Production Planning & Control International Journal
  240. Switching clocks in Xilinx / Altera devices
  241. nios-run: waiting for target.......?
  242. New WinFilter Digital Filter design freeware tool release available.
  243. Cyclone Memory Development Board
  244. Gate Count vs Logic Element (LE)
  245. 1GHz FPGA counters
  246. Modelsim: No default binding for component
  247. Image export from Quartus?
  248. VHDL model of Xilinx's Rocket I/O MGT
  249. VHDL
  250. EDA software&IP core