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  1. Generating SVF files from Quartus?
  2. Problem with the SOPC-Builder from Altera
  3. spartan-3 sram
  4. Non-global location constraints in Xilinx/XST using VHDL
  5. Problem with Xilinx Webpack documentation
  6. ISE 6.3 Suse 9.1 installation problem
  7. How To Synchronize FPGAs
  8. edge reset
  9. Using C++ on NIOS
  10. VHDL gate level from Xilinx XST
  11. Re: XST vhdl adder with carry out : broken carry chain
  12. Spartan-3 DDR Speed
  13. Bodged up 10/100 Ethernet & USB on FPGA.
  14. combinatorial loops / feedback paths discussion
  15. From whence the MAC on an Altera NIOS devel kit board?
  16. Microblaze:ISE-EDK
  17. Understanding output width in signed multipliers
  18. ISE and Ba*** for Linux?
  19. Tcl script window does not appear
  20. Getting started with Altera IP Core
  21. bad nph file
  22. Multiple Clockdomains in Handel-C
  23. Stratix II vs. Virtex 4 - power
  24. Ring Oscillator Redux
  25. Stratix II vs. Virtex 4 - features and performance
  26. Stratix II vs. Virtex 4 - availability & fab partnership
  27. Virtex 4 integrated A/Ds?
  28. Altera Max II
  29. Modelsim wave viewing in batch mode
  30. question about Webpack - PACE
  31. MAX7000 power-up state
  32. How feasible is a SoC project?
  33. AHB_SLAVE
  34. Bi Dir Synthesis Problem in Quartus?
  35. RocketIO simulation w ISE6.2iSP3 and VCS-7.1.1 under Linux
  36. ISP PROM's : PROM programming fails
  37. How intimidating is Xilinx's EDK?
  38. Where are the Cyclones2
  39. Virtex-4 development boards
  40. doing 'slow' calculations in verilog
  41. Please help me find the source of this glossary
  42. Reconfigure Spartan 3 without losing BRAM?
  43. gigabit ethernet
  44. "don't cares" on ibuf output
  45. AREA_GROUP and Modular Design Flow
  46. Verilog vs VHDL for Loops
  47. Atmel DK2 kit
  48. Verilog books
  49. Statix II vs. Virtex 4
  50. FPGA with PCI interface for video processing?
  51. EPM7160SLC84 ex-stock in UK?
  52. How can i interface Spartan-3 with PC/104.
  53. Xilinx EDK & IPIF performance
  54. How to enable connecting floating input pins to constants?
  55. Routing Resources
  56. XCF32P availability
  57. Regarding FPGA
  58. beginner's question
  59. PLL in CPLD
  60. xdl tool, or Xilinx Design Language
  61. Problem with I/O state while power on
  62. USER RESET in XILINX FPGA
  63. Twister + Lancelot
  64. Xilinx Prototype Board with CAN controller
  65. Burning Questions- FPGA architecture, packing, LUTs....
  66. Quartus In-system Memory bug
  67. VHDL Design for running sorter
  68. Synthesis problems with while and non-constant terminal point.
  69. Handel C writing to flash ram & sampling hey guys clock setting
  70. Programming Altera Config Device
  71. Looking for a Design for a Small FPGA Board
  72. adder VS increment
  73. problem with ALtera CPLD
  74. standalone operation of ISE text editor or MTI text editor
  75. question about types in VHDL
  76. I/O state of max7000s during power-up?
  77. altera quartus II handbook is wrong??
  78. Simulation Warning
  79. CLK2X
  80. Xilinx Core Gen Question
  81. New VHDL (Xilinx) Website
  82. constraints coverage
  83. Synthesis issues in Modelsim 5,7g SE for a simple ROM
  84. EDK OPB Uart 16550
  85. Xilinx RocketPHY Development Kit (HWK-RPHY-DVLP)
  86. HIS 2004 - Special Session on Architecture for Neuro-Fuzzy Controllers - 15/10/2004
  87. Help with Coregen ROM in ISE 6.2.03i
  88. Xilinx S3 Serial Port Code
  89. ERSA low cost BGA assembly system?
  90. test (empty)
  91. Spartan 2E gets hot after configuration
  92. EDK
  93. Adding a Delay2
  94. clock divider
  95. is there a way to convert ALTERA MAXPLUS GDF file to LATTICE file?
  96. Unwanted shift in multiplier
  97. AHB-Slave
  98. Can ACEX work well in high EMI environment?
  99. 6$ into $10 000? THIS REALLY WORKS!!!!
  100. spartan-3 I/O timing
  101. Would flash/antifuse-based vendors be more likely to disclosebitstream formats?
  102. two questions about spartan/xilinx devices??
  103. Virtex 4 released today
  104. New to Xilinx Software - help with downlaod
  105. ML300 Ethernet question.
  106. Xilinx EDK and plb master
  107. JTAG Prog. and Power Requirments
  108. Questions about clocks on the Cyclone Nios development board
  109. Adding a Delay
  110. Newbie question systemc
  111. Bus Frequecy in virtex2p powerpc
  112. altera stratix II dev boards
  113. JBits 3.0 and Virtex-II Pro
  114. Need some help with some technical claims...
  115. MAX II CPLD(fpga ?) Board
  116. Xilinx ISE vs. SuSE Linux 9.x
  117. std_logic_textio - in xilinx
  118. delivering VHDL (RTL) IP core to my customer: how ?
  119. New to FpGa ; At configuring the device error cmes
  120. Simple FPGA board
  121. Simulation probs with Altera LPM_FIFO+
  122. Placement vs Map in 6.2i, sp3
  123. AD: ACEX 1K50 FPGA board clearance sale
  124. Two questions about FFs
  125. Problem with timing in post PAR with Xilinx Virtex II
  126. new to fpga
  127. [OT] International Foundation for Terror Act Victims in Beslan
  128. Picoblaze VHDL Code Block diagram
  129. JTAG Connection For PPC Using VisonProbe V2PRO V2P30
  130. Memory access time?
  131. Problem with HELP after installation of Webpack ISE
  132. AMBA AHB
  133. Initializing on-board memory on V2MB100 development board
  134. Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
  135. ISE 6.2 - Bug or folly?
  136. Initializing memory from a testbench
  137. HELP : need an old version Xilinx software key -> Alliance Serie 2.1i !
  138. PCB CADENCE ORCAD 2004 - 2000, Altium P-CAD V2002, DXP SUITE V2004, WEBSPHERE EVERYPLACE MOBILE PORTAL v5.0 (c) ALTIUM [2 CDs], ModelSim.SE.v6.0, AutoTRAX.EDA.v3.04, Aldec.Riviera.v2004.08.1533.WinNT2kXP, Metrowerks CodeWarrior Development Studio v
  139. EDIF generation from Verilog in ISE 6.2i
  140. vhdl error ?? - [code included]
  141. i2c-core from opencores.org
  142. How to use Windpower ICE with Virtex2Pro V2P4 FG456 board from Memec
  143. SignalTapII influencing timing of design?
  144. why systemc?
  145. how to get the data from ADC
  146. Quartus2 4.1 SP1 Hangs
  147. Altera DDR SDRAM & external DSP
  148. Re: Xilinx Xpower Issues - Help from xilinx team please
  149. Quartus2 V4.1 SP1
  150. Installing Ba***
  151. EDK 3.2 and modelsim ppc simulation
  152. VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
  153. How to purposely make pipelining in Handel-C?
  154. how to get the data from ADC
  155. DDR2 SDRAM and Virtex2Pro
  156. A Typical Design Cycle
  157. Altera Master Peripheral & Avalon Bus Timing?
  158. I NEED HELP / MENTOR
  159. Quartus II and MAX7000S unused pins
  160. Altera Quartus FSM Simulation Delay?
  161. OD/OC outputs with Xilinx Spartan II
  162. Xilinx PCI Express Solution: 2 Questions.
  163. Need assistance with an FPGA based project.
  164. VHDL modelling USB device
  165. Interfacing an 1GS ADC
  166. cypress's 32bit pci target reference design?
  167. PCI Noise
  168. PDSPs vs FPGAs for DSP
  169. more than one clock
  170. IEEE ICM'2004 last Call For Papers
  171. Xilinx Xpower Issues - Help from xilinx team please
  172. Is Stratix-II ALM some kind of partitionable LUT
  173. [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
  174. CPLD : Is there a way
  175. Fanout Xilinx
  176. ADC unit with 2 input channels, 12 bit, 10MHz conversion rate, 4Ksamples FIFO, USB (or PCI on PC104+ form) interface, Linux, QNX driver
  177. spartan3 pci above 33MHz
  178. Unisim Library
  179. Re: vga to ethernet converter
  180. Completed my first Virtex4 design
  181. the pci signal
  182. StateCad, IO vector question.
  183. reg: clock generatred by combinational logic
  184. the global output enable pins of lattice ispxpld 5000mv
  185. Xilinx XQ4036-3PG411 problem
  186. ISO Low cost Fpga / high I/O rate (so prob spartan3 pci/USB2 solution)
  187. Xpower - Clock Power
  188. Spartan 3 Starter Kit and ISE WebPACK
  189. virtex II on pci bus devboard
  190. Programming using .pof File and In-system Programming
  191. spartan 2 vs Spartan 3
  192. Sentinel dongle no longer detected by Quartus
  193. MGT
  194. Synthesize verilog code with Icarus for Spartan?
  195. VirtexII Pro Evaluation Kit from Avnet
  196. Altera LVDS Transceiver Megafunction - ALTLVDS - question
  197. From good-old ISA bus cards to PCI bus
  198. Ann: Link-list to FPGA related topics / sites
  199. modelsim and rocketio
  200. Installing Xilinx ISEWebPack under Wine
  201. Test
  202. FPGA Floating Point Multiplier Design
  203. PCI-Core
  204. ISE EDIF export
  205. Delay Modelling in TVPACK
  206. The Effect of Pin Assginment
  207. Floorplanner RPM question
  208. EDK core wrapping and include files
  209. Nios Development Kit, STRATIX Edition
  210. how can I simulate the vhdl and verilog mixed design in modelsim?
  211. Counter counting on both clock edges.
  212. SOC and ASIC ?
  213. PLB above 100MHz ?
  214. 16-depth FIFO and 64-depth FIFO use the same Ram
  215. Problems With Spartan 3 Starter Board
  216. Channel Link signals into Xilinx
  217. Newbie question--> Obtaining RTL netlist from Xilinx ISE 6.2i Project navigator
  218. using GNU to compile for PPC405?
  219. Xilinx Spartan 3 DCM/DFS
  220. Impact vs. Linux RedHat Linux
  221. How to Figure out EPLD can be socketed or not!
  222. FPGA Board Newsletter August 2004
  223. Replace for Altera ByteBlaster II -- Minford MF160 FPGA and CPLD Downloader
  224. Test : Test Message
  225. DSP & FPGA Resource Guide
  226. Modelsim: ROM initialisation
  227. Xilinx XC9572XL delay prediction
  228. Xilinx Spartan II and 5V PCI
  229. Xilinx DCM Spread Spectrum feature
  230. problem with DDR
  231. PP1000SetupDMAChannel( ) function in celoxica RC1000
  232. Xilinx Command Prompt
  233. EPM7064LC44-7 - Not there in Quartus II...
  234. X propagation in Timing Simulation
  235. JTAG software
  236. Nios IRQ lockup
  237. ring oscillator calibration
  238. Altera Quartus II 4.1 double-click on QPF-File doesn't work
  239. 6.1 vs. 6.2
  240. Configuration : Virtex-E, CLB column
  241. Re: Xilinx version ROM with automatic increment
  242. Xilinx version ROM with automatic increment
  243. XST 5 input mux synthesis question
  244. IP Coregen: FFT v2.1 IP core regd.
  245. Any experience with Actel Flash-FPGAs ?
  246. FPGA SPARTAN 3 or 2 BOARD SCHEMATIC protel
  247. Xilinx in Linux
  248. Maximum allowable ground bounce for xilinx fpgas
  249. DDR SDRAM
  250. Altera MAX II