- Real numbered operations
- Chipscope Core Generator:VIO
- Back-Annotate Assignments
- bufgmux
- unstable fpga design
- Anyone routing signals between balls in FBGA?
- Question for XST expert
- counter skrews up design
- Active Rece\onfiguration of Xilinx FPGAs
- How To Provide External Input & Output To Startix 1S40..?
- Simultaneously Switching Outputs in Spartan-II
- Virtex-4 Slower than V2Pro?
- direction of carry and shift chains in xilinx & Altera
- alternatives to xst-map
- Experiences with SPARTAN3?
- Feeding PLL
- location of Stratix primitives list
- FPGA Design Consultant/Contractor Needed
- Xilinx Virtex II MAC & PHY. ( HELP)
- Constrained Random Value in verilog
- Internal Capture of clock in FPGA
- Modelsim simulation problem
- Virtex-4: DSP48 Fmax missing?
- NI*S II-verilog in Virtex FPGA
- How to transfer Xilinx .vhd back to .vhw/.tbw?
- M: Käyttövalmis 1581-klooni
- how to transfer Xilinx .vhd back to .vhw/.tbw?
- Re: JOP on Spartan-3 Starter Kit
- a pci implemenation problem, thanks
- Does Xilinx XST plan on supporting `define macro( X ) ?
- What was the first FPGA?
- POKER
- ModelSim
- BCD to bin convertor
- How can FPGAs be used for high speed data acquisition????
- How can FPGAs be used for high speed data acquisition????
- What is role of place & route tools in synthesis in vhdl.& HOW THE AREA & time constrain are specifiesd in XIlinx or modelsim software?
- How many Altera LE's to Xilinx Slices????
- XAPP253
- SPARTANI II - PCI target logic - what code generates burst read ?
- which xilinx CPLD to select?
- ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
- Quartus 4.0, Excalibur Synthesis problem
- ISE 6.2 EDF mapping problem
- Question on Xilinx VirtexPro II FPGA chip... please
- WebPACK post-PAR min clock period?
- programming a LC5512MB using the IEEE1532 extension
- Metastability pipeline causes bad juju
- Xilinx to Make Image Processing FPGA
- Xilinx VirtexE internal oscillator
- Xilinx 6.2sp3: Post Place and Route Modelsim6.0 Simulation Crashes
- Same Bitstream: Different Performance
- ChipScope Pro : Data Samples and No of Trigger Occurences
- Where to buy cheap MAXII CPLD?
- EMAC ping Board
- Where can I buy Cheap MAX II CPLD?
- [Noise] Xilinx Evaluation Board Problem
- Tristate
- Avnet Virtex 2 Pro Dev. Kit
- Xininx XC2V6000 Eval board for 1517 BGA Package
- 1.2V
- Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool
- simprim errors
- spartan 3 on 4 layers
- HDL-Models of CLB/Slice
- Interfacing from the analogue domain
- level converter for high frequencies
- EP1C12 or XC3S400?
- Initializing Block Ram of a partial Bitstream
- xilinx VP20 and SDRAM
- direct calculation of the modulus ?
- Hve to know the pin connection between cpld and fpga in my design
- Reading RAM while
- DCM for generating higher frequencies.
- MicroBlaze Platform simulator is available (can run uCLinux!)
- newbie question
- post place and route issues for a generic simple n input and gate
- Re: CAche memory
- multiplexing clocks
- Student SATA project
- GLKP and GLKS
- Xilinx Spartan3 config problem
- low cost MPEG4 codec (from Atmel )
- Unguided slices
- Multiple Access on long lines
- CORDIC NCO Frequency resolution?
- Actel Fusefile Reverse Engineering
- Routing PLL output
- Problem in Constraining Routing in Xilinx PAR
- VHDL help needed ($)
- Temperature considerations of inactive logic blocks
- MXE post-translate simulation problem
- VHDL code for Type and Components
- Newbie, Altera vs Xilinx
- Xilinx : Memory-Compiler for DDR-1
- Coregen difficulties with DCT
- Daft RapidIO question
- RapidIO functional simulation
- Use Xilinx VP20 with 2 ppc and one DRAM chip
- Spartan 3 Kit
- PPC cores and XAUI core on Xilinx Virtex-II Pro 20
- Sine function implementation in FPGA
- Daft modelsim question
- 3.3 V ref VCC on Xilinx AFX FF1152 board?
- Flex10K10A, I2C, MultiVolt IO, pull-ups
- Xilinx DCM and Timing Constraints
- Xilinx lead free parts hidden fact
- add/sub 2:1 mux and ena in a single LE (Cyclone)
- PLL lock usage into Altera Stratix devices
- modelsim crashs with large ram simulation model
- Synplify on Fedora C2
- International Workshop on Applied Reconfigurable Computing (ARC): 2nd call for papers
- XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
- Unused pins
- spartan 3 starter kit
- JBits and Spartan
- Advice for a Beginner?
- Xilinx ISE 6.3i 'include construct issue
- FPGA not turning off
- 64 bit version of xilinx ISE
- DCM and CLKFX - is this allowed?
- FSL State machine to read data in
- Is the Xilinx's silicon better than Altera's?
- Changing clock domain
- Constant instantiation
- Crossing clock domain issue at Functional Simulation
- ActGen to use or not to use?
- Ripple counter ?
- PCI Transactor
- Sine function implementation in FPGA??
- 8-bit word to 4-digit, 7-segment display
- Xilinx Multiple Clock Domains
- Hash algorithm for hardware?
- HOw to use Xilinx Virtex-II Pro to read and write FLASH
- How to use Xilinx Virtex-II Pro to read and write NAND FLASH.
- Features of Xilinx ISE WebPACK & Altera's Quartus II.
- Re: 8086 IP-core in VHDL
- Archiving QuartusII project
- Help on test RocketIO loopback
- I need help for Xilinx Demo Board (XC40xx-PC84
- question on interfacing FPGA with a sensor
- Is it possible to Reverse-Engineer an FPGA Output file?
- FSL Read Data Out Problem
- Asynchronous reset timing problem
- meaning of "field-programmable" in FPGA
- Chipscope and BlockRam
- XC2V1000 Block RAM size
- does ISE 6.3 improve timing vs. ISE 6.2 ?
- Help with old CUPL Ver 4.7A
- Uploading data to the DDR memory on the ML300 board
- Xilinx FPGA EMAC Drivers
- M*Blaze in Cyclone ! End of What? ;)
- Xilinx Virtex II and EMAC
- XST - undeterministic synthesis
- FPGA servo motor controller
- best way to perform multiplies in vhdl
- Hardware Log and EXP
- Floating Point Powers and Logs?
- XPower help.
- How to generate a signal on Xilinx Spartan II
- xilina altera competing history
- FPGA+ggiabit ethernet and protocols
- Open-Source MicroBlaze IP-Core working in FPGA :)
- Removing set/reset logic for shift register (HDL ADVISOR )
- COMMA_ALIGN_MSB being ignored?
- JOP on Spartan-3 Starter Kit
- FSL link beginner question
- Windowsdriver for the Cypress USB-Chip SL811
- unbreakable conmbination cycle in Handel C
- System Generator.
- Wang Nam
- Xilinx SRL16 example
- FPGA vs ASIC area
- ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
- A better way to do embedded Floating point?
- test post
- EDK FSL Example
- Programming Cyclone 1C20 board
- Enabling clock generation
- Xilinx SRL16 test
- Cheaper way to get Xilinx Core generator
- Pricing info for Synplify Pro Xilinx...
- Evaluation Board for Xilinx Virtex
- VHDL Project Verilog open core compatibility?
- FPGA for OCR processing
- [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
- Xilinx Timing Constraints
- Virtex-II : Architecture
- Chipscope Pro and VHDL
- Clock Edge notation
- PSL pros and cons
- Content of RAM in Modelsim
- Read back FPGA configuration
- luts are optimized away
- FPGAs as a PCI (target) controller
- Microblaze : ilmb_Cntrl
- Quartus II annoyance
- suggestions for Xilinx tool enhancements
- Re: How to get 27MHz from 10 MHz in FPGA???
- Xilinx Constraints
- Xilinx FIFOs
- Xilinx Read First Write First
- Co-Processor for Microblaze or PowerPC Processor
- Boot : Sram Problem
- XST Tool - Want a verilog simulation netlist
- MicroBlaze is no available as Open-Source!! (from independant 3rd party)
- fast adder and equal
- Altera Apex20KE -x pll problem
- NV on-chip memory?
- Quartus and VDHL misbehavior
- has anyone tried implementing Serpent?
- what to do with the DCM locked signal?
- Call for Participation, ICFPT04, Brisbane 6-8 December
- Simple Counter in Verilog
- MicroBlaze & SRAM
- problems about Behavioral Compiler
- Maybe someone knows where I can get a schematic of the MJL Cyclone Development Kit board? Thx.
- MAX7000s GCLRn Pin input current?
- virtex2.components.all
- embedded linux on FPGA?
- AVNET's Xilinx prototyping modules (AvBus cable?!?)
- VHDL inout used for non bidirectional uses
- XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
- Xilinx ISE 6.2i WebPack & project restoration
- PCI FPGA Dev kits/SOPC boards
- xilinx spice models
- Altera SDRAM controller - Only 2 words burst???
- HDL Behaviorial Model for an LCD Controller
- india jobs ;->
- Nios Addressing
- Getting info from a digital line
- bin hot gray jedi encoding in ISE
- VxWorks and Xilinx Virtex-II Pro
- NIOS II (full sample working with DMA in HAL)?
- Webpack 6.3 and Spartan3-1000/1500?
- High speed counters on Xilinx CoolRunner-II
- New HDLmaker release, Virtex4 support added
- equal to zero
- MUXCY and XORCY local outputs (LO)
- Spartan-3 VCCIO ramp up time
- Why are there 2 clock supplies in Nios Apex board proto-connectors
- Cyclone FPGA as Cardbus controller
- How to design a programming parallel cable
- Xilinx ISE and Verilog $signed/$unsigned tasks?
- using both edges of clocks in a design - effects on synthesis
- Quartus II v4.1 & GNU
- Can Map and Par still handle the XC4000e family?
- NIOS II / Cyclone II - Multiply, Barrel Shift and Divide
- [ALTERA] NIOS-II + MMU + FPU
- 5V Tolerant?