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  1. Real numbered operations
  2. Chipscope Core Generator:VIO
  3. Back-Annotate Assignments
  4. bufgmux
  5. unstable fpga design
  6. Anyone routing signals between balls in FBGA?
  7. Question for XST expert
  8. counter skrews up design
  9. Active Rece\onfiguration of Xilinx FPGAs
  10. How To Provide External Input & Output To Startix 1S40..?
  11. Simultaneously Switching Outputs in Spartan-II
  12. Virtex-4 Slower than V2Pro?
  13. direction of carry and shift chains in xilinx & Altera
  14. alternatives to xst-map
  15. Experiences with SPARTAN3?
  16. Feeding PLL
  17. location of Stratix primitives list
  18. FPGA Design Consultant/Contractor Needed
  19. Xilinx Virtex II MAC & PHY. ( HELP)
  20. Constrained Random Value in verilog
  21. Internal Capture of clock in FPGA
  22. Modelsim simulation problem
  23. Virtex-4: DSP48 Fmax missing?
  24. NI*S II-verilog in Virtex FPGA
  25. How to transfer Xilinx .vhd back to .vhw/.tbw?
  26. M: Käyttövalmis 1581-klooni
  27. how to transfer Xilinx .vhd back to .vhw/.tbw?
  28. Re: JOP on Spartan-3 Starter Kit
  29. a pci implemenation problem, thanks
  30. Does Xilinx XST plan on supporting `define macro( X ) ?
  31. What was the first FPGA?
  32. POKER
  33. ModelSim
  34. BCD to bin convertor
  35. How can FPGAs be used for high speed data acquisition????
  36. How can FPGAs be used for high speed data acquisition????
  37. What is role of place & route tools in synthesis in vhdl.& HOW THE AREA & time constrain are specifiesd in XIlinx or modelsim software?
  38. How many Altera LE's to Xilinx Slices????
  39. XAPP253
  40. SPARTANI II - PCI target logic - what code generates burst read ?
  41. which xilinx CPLD to select?
  42. ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
  43. Quartus 4.0, Excalibur Synthesis problem
  44. ISE 6.2 EDF mapping problem
  45. Question on Xilinx VirtexPro II FPGA chip... please
  46. WebPACK post-PAR min clock period?
  47. programming a LC5512MB using the IEEE1532 extension
  48. Metastability pipeline causes bad juju
  49. Xilinx to Make Image Processing FPGA
  50. Xilinx VirtexE internal oscillator
  51. Xilinx 6.2sp3: Post Place and Route Modelsim6.0 Simulation Crashes
  52. Same Bitstream: Different Performance
  53. ChipScope Pro : Data Samples and No of Trigger Occurences
  54. Where to buy cheap MAXII CPLD?
  55. EMAC ping Board
  56. Where can I buy Cheap MAX II CPLD?
  57. [Noise] Xilinx Evaluation Board Problem
  58. Tristate
  59. Avnet Virtex 2 Pro Dev. Kit
  60. Xininx XC2V6000 Eval board for 1517 BGA Package
  61. 1.2V
  62. Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool
  63. simprim errors
  64. spartan 3 on 4 layers
  65. HDL-Models of CLB/Slice
  66. Interfacing from the analogue domain
  67. level converter for high frequencies
  68. EP1C12 or XC3S400?
  69. Initializing Block Ram of a partial Bitstream
  70. xilinx VP20 and SDRAM
  71. direct calculation of the modulus ?
  72. Hve to know the pin connection between cpld and fpga in my design
  73. Reading RAM while
  74. DCM for generating higher frequencies.
  75. MicroBlaze Platform simulator is available (can run uCLinux!)
  76. newbie question
  77. post place and route issues for a generic simple n input and gate
  78. Re: CAche memory
  79. multiplexing clocks
  80. Student SATA project
  81. GLKP and GLKS
  82. Xilinx Spartan3 config problem
  83. low cost MPEG4 codec (from Atmel )
  84. Unguided slices
  85. Multiple Access on long lines
  86. CORDIC NCO Frequency resolution?
  87. Actel Fusefile Reverse Engineering
  88. Routing PLL output
  89. Problem in Constraining Routing in Xilinx PAR
  90. VHDL help needed ($)
  91. Temperature considerations of inactive logic blocks
  92. MXE post-translate simulation problem
  93. VHDL code for Type and Components
  94. Newbie, Altera vs Xilinx
  95. Xilinx : Memory-Compiler for DDR-1
  96. Coregen difficulties with DCT
  97. Daft RapidIO question
  98. RapidIO functional simulation
  99. Use Xilinx VP20 with 2 ppc and one DRAM chip
  100. Spartan 3 Kit
  101. PPC cores and XAUI core on Xilinx Virtex-II Pro 20
  102. Sine function implementation in FPGA
  103. Daft modelsim question
  104. 3.3 V ref VCC on Xilinx AFX FF1152 board?
  105. Flex10K10A, I2C, MultiVolt IO, pull-ups
  106. Xilinx DCM and Timing Constraints
  107. Xilinx lead free parts hidden fact
  108. add/sub 2:1 mux and ena in a single LE (Cyclone)
  109. PLL lock usage into Altera Stratix devices
  110. modelsim crashs with large ram simulation model
  111. Synplify on Fedora C2
  112. International Workshop on Applied Reconfigurable Computing (ARC): 2nd call for papers
  113. XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
  114. Unused pins
  115. spartan 3 starter kit
  116. JBits and Spartan
  117. Advice for a Beginner?
  118. Xilinx ISE 6.3i 'include construct issue
  119. FPGA not turning off
  120. 64 bit version of xilinx ISE
  121. DCM and CLKFX - is this allowed?
  122. FSL State machine to read data in
  123. Is the Xilinx's silicon better than Altera's?
  124. Changing clock domain
  125. Constant instantiation
  126. Crossing clock domain issue at Functional Simulation
  127. ActGen to use or not to use?
  128. Ripple counter ?
  129. PCI Transactor
  130. Sine function implementation in FPGA??
  131. 8-bit word to 4-digit, 7-segment display
  132. Xilinx Multiple Clock Domains
  133. Hash algorithm for hardware?
  134. HOw to use Xilinx Virtex-II Pro to read and write FLASH
  135. How to use Xilinx Virtex-II Pro to read and write NAND FLASH.
  136. Features of Xilinx ISE WebPACK & Altera's Quartus II.
  137. Re: 8086 IP-core in VHDL
  138. Archiving QuartusII project
  139. Help on test RocketIO loopback
  140. I need help for Xilinx Demo Board (XC40xx-PC84
  141. question on interfacing FPGA with a sensor
  142. Is it possible to Reverse-Engineer an FPGA Output file?
  143. FSL Read Data Out Problem
  144. Asynchronous reset timing problem
  145. meaning of "field-programmable" in FPGA
  146. Chipscope and BlockRam
  147. XC2V1000 Block RAM size
  148. does ISE 6.3 improve timing vs. ISE 6.2 ?
  149. Help with old CUPL Ver 4.7A
  150. Uploading data to the DDR memory on the ML300 board
  151. Xilinx FPGA EMAC Drivers
  152. M*Blaze in Cyclone ! End of What? ;)
  153. Xilinx Virtex II and EMAC
  154. XST - undeterministic synthesis
  155. FPGA servo motor controller
  156. best way to perform multiplies in vhdl
  157. Hardware Log and EXP
  158. Floating Point Powers and Logs?
  159. XPower help.
  160. How to generate a signal on Xilinx Spartan II
  161. xilina altera competing history
  162. FPGA+ggiabit ethernet and protocols
  163. Open-Source MicroBlaze IP-Core working in FPGA :)
  164. Removing set/reset logic for shift register (HDL ADVISOR )
  165. COMMA_ALIGN_MSB being ignored?
  166. JOP on Spartan-3 Starter Kit
  167. FSL link beginner question
  168. Windowsdriver for the Cypress USB-Chip SL811
  169. unbreakable conmbination cycle in Handel C
  170. System Generator.
  171. Wang Nam
  172. Xilinx SRL16 example
  173. FPGA vs ASIC area
  174. ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
  175. A better way to do embedded Floating point?
  176. test post
  177. EDK FSL Example
  178. Programming Cyclone 1C20 board
  179. Enabling clock generation
  180. Xilinx SRL16 test
  181. Cheaper way to get Xilinx Core generator
  182. Pricing info for Synplify Pro Xilinx...
  183. Evaluation Board for Xilinx Virtex
  184. VHDL Project Verilog open core compatibility?
  185. FPGA for OCR processing
  186. [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
  187. Xilinx Timing Constraints
  188. Virtex-II : Architecture
  189. Chipscope Pro and VHDL
  190. Clock Edge notation
  191. PSL pros and cons
  192. Content of RAM in Modelsim
  193. Read back FPGA configuration
  194. luts are optimized away
  195. FPGAs as a PCI (target) controller
  196. Microblaze : ilmb_Cntrl
  197. Quartus II annoyance
  198. suggestions for Xilinx tool enhancements
  199. Re: How to get 27MHz from 10 MHz in FPGA???
  200. Xilinx Constraints
  201. Xilinx FIFOs
  202. Xilinx Read First Write First
  203. Co-Processor for Microblaze or PowerPC Processor
  204. Boot : Sram Problem
  205. XST Tool - Want a verilog simulation netlist
  206. MicroBlaze is no available as Open-Source!! (from independant 3rd party)
  207. fast adder and equal
  208. Altera Apex20KE -x pll problem
  209. NV on-chip memory?
  210. Quartus and VDHL misbehavior
  211. has anyone tried implementing Serpent?
  212. what to do with the DCM locked signal?
  213. Call for Participation, ICFPT04, Brisbane 6-8 December
  214. Simple Counter in Verilog
  215. MicroBlaze & SRAM
  216. problems about Behavioral Compiler
  217. Maybe someone knows where I can get a schematic of the MJL Cyclone Development Kit board? Thx.
  218. MAX7000s GCLRn Pin input current?
  219. virtex2.components.all
  220. embedded linux on FPGA?
  221. AVNET's Xilinx prototyping modules (AvBus cable?!?)
  222. VHDL inout used for non bidirectional uses
  223. XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
  224. Xilinx ISE 6.2i WebPack & project restoration
  225. PCI FPGA Dev kits/SOPC boards
  226. xilinx spice models
  227. Altera SDRAM controller - Only 2 words burst???
  228. HDL Behaviorial Model for an LCD Controller
  229. india jobs ;->
  230. Nios Addressing
  231. Getting info from a digital line
  232. bin hot gray jedi encoding in ISE
  233. VxWorks and Xilinx Virtex-II Pro
  234. NIOS II (full sample working with DMA in HAL)?
  235. Webpack 6.3 and Spartan3-1000/1500?
  236. High speed counters on Xilinx CoolRunner-II
  237. New HDLmaker release, Virtex4 support added
  238. equal to zero
  239. MUXCY and XORCY local outputs (LO)
  240. Spartan-3 VCCIO ramp up time
  241. Why are there 2 clock supplies in Nios Apex board proto-connectors
  242. Cyclone FPGA as Cardbus controller
  243. How to design a programming parallel cable
  244. Xilinx ISE and Verilog $signed/$unsigned tasks?
  245. using both edges of clocks in a design - effects on synthesis
  246. Quartus II v4.1 & GNU
  247. Can Map and Par still handle the XC4000e family?
  248. NIOS II / Cyclone II - Multiply, Barrel Shift and Divide
  249. [ALTERA] NIOS-II + MMU + FPU
  250. 5V Tolerant?