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  1. Spartan 3L - misleading info to potential customers
  2. Favourite Design Entry Optomisation Method?
  3. xc3sprog and nuhorizons
  4. UTLB has been flush invalidated - Modelsim warning
  5. Xilinx Multimedia Board
  6. TSMC release 40V 0.18u process, MTP comming
  7. Quartus II: trace
  8. Help! What is this card?
  9. EDK 6.3i "Entry Point Not Found" error
  10. Beginers Question ModelSim Signals
  11. Xilinx OPB custom interface
  12. JOP on Trenz Retrocomputiong Board
  13. Low cost million gate Spartan 3 board?
  14. DDR SDRAM with Xilinx Virtex 2 on self designed PCB
  15. Modelsim library problem
  16. VLSI professional at NASA
  17. Spartan 3 output voltage level
  18. Xilinx EDK Simulation - Unresolved references
  19. I found this great little site
  20. Xilinx S3 IO during programming latches Cypress FX2 Reset
  21. Altera chip identification
  22. How to get the PPC profiler to work in Xilinx VP2 platform?
  23. 18x18 Multipliers - Spartan III
  24. Microblaze: reading files using sysace compactflash
  25. FPGA development board
  26. 5V PCI interface using Spartan3
  27. Xilinx EDK - Unable to initialize BRAM in Simulation
  28. Custom Megafunctions in Quartus II
  29. RocketIO success?
  30. Performance of Xilinx System Generator RTL?
  31. nucleus
  32. microblaze: execute program from external memory
  33. NIOSII problems?
  34. Ordering Xilinx Ba*** software for Linux
  35. Pci timing tsu and tco
  36. Spartan-3 configuring problem
  37. --New-- ArmXF ARM+FPGA Blocks Development Platform
  38. Vccaux on Spartan 3
  39. Async and sync resets
  40. Newbie FPGA Qs
  41. Setup violation warning with constant signal in Modelsim/Webpack
  42. ISO Free cores repository
  43. 5V inputs with series resistor on Spartan-3
  44. Xilinx, VHDL, Verilog, ModelSim, BMP
  45. ModelSim
  46. 35487 Mining the Web :Searches with Kriging, Inverse DistanceWeighting, eigenVectors and Cross-Pollination 35487
  47. Suggestion for Xilinx parallel port cable replacement.
  48. Xilinx EDK 6.3 : DDR Burst Mode
  49. Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
  50. Extending chipscope capture memory by using external async SRAM
  51. OpenCore USB 2.0
  52. New Xilinx 6.3i from Prentice Hall ?
  53. JTAG boundary scan xc2v6000
  54. RocketIO clock recovery
  55. Help with Virtex II and 5v TTL
  56. Neural nets
  57. Soft Processor Core
  58. LPM_MODOLUS warning
  59. IO pins : short circuit protection ?
  60. Electronica 2004 - munich - Altera ???
  61. Gap between layers in PCB
  62. DMA for PPC in Virtex-II Pro/EDK6.2
  63. Driving towards 2V4000 during Power up
  64. video camera interface to FPGA
  65. Digital LP filter in multiplier free FPGA
  66. Virtex-II Pro Dev Board for RTOS Integrity
  67. FPGA's at Electronica 2004
  68. PWM using FPGA
  69. Attention All Housewives: Here is Great Business
  70. Spartan3 Block RAM from WebPACK
  71. Basic DVI example?
  72. Obsolete processors resurected in FPGAs
  73. std_logic_vector(0 downto 0)
  74. Virtex-II Pro Dev Board for RTOS Integrity
  75. Demote assignments
  76. Why does NCVerilog fail to annotate these timing checks?
  77. DualPortRAM serial IN - parallel OUT
  78. I can't set inout port in vhdl code
  79. asynchronous bus transfers
  80. Virtex2P: lock down DCM and Global buffer
  81. digital analog conversion
  82. Internal architecture of lut
  83. Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
  84. about ISE6.2.03 module design
  85. Problem with PLL ?
  86. Rocket IOs and Infiniband protocol
  87. VHDL is correct but when burn into chip is not correct. Help me to solve this problem please
  88. multiplexer / serdes
  89. Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
  90. DDR Mux - how does it work?
  91. Xilinx Tshirts in football package.....
  92. Timing Issues in Quartus design
  93. Advice on Contemporary Low cost, Medium Density CPLDs
  94. VirtexII-Pro MGT: 8/10 coding bypass problems
  95. Virtex2Pro config question
  96. SpartanII + ARM7 Question
  97. Overshoot/undershoot towards 2V4000
  98. Research Project Re: Graphics Processor
  99. Best Home Base Work
  100. xilinx webpack simulation problem (latch in place of logic)
  101. module based partial reconfiguration questions
  102. Where to find very basic FPGAs
  103. C Compiler for Picoblaze !!!!!
  104. Accessing rows in bank
  105. FPGA as "Differential SSTL_2" clock driver
  106. [ANN] InFormal 0.1.1 Released
  107. Performing floating point in VHDL
  108. Spartan 3 reverse recovery time
  109. Postdoctoral position available
  110. diode recovery time for Spartan 3
  111. alpha data v2 ADP-DRC-II board
  112. xilinx software licenses and updates
  113. ISE problems with Linux
  114. SDRAM sustained bursts
  115. QuartusII, Flex10K & fan-out
  116. Partial reconfiguration, Special kind of bus macro
  117. Re: Stupid Americans! -- Stupid... Stupid... STUPID!!! _____________---_ zasbep
  118. SRAM to be able to read/write Micron SDRAM
  119. XST Question
  120. Personality Module (Z-Dok) proto board for ML310
  121. SpartanII + ARM7 Question
  122. Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have tool
  123. Fifo problem in Cyclone devices
  124. Mixed RTL ,XILINX EDK
  125. what's the scenario out there
  126. FPGA Network Encryption Engine
  127. Programming XCR3064(Xilinx) or ZR3064 (Philips)
  128. Proteus 6 Professional, labcenter.co.uk, IAR visualSTATE v5.0.7.88, IAR Embedded.Workbench for 68HC12.V2.44A, ARM.V4.11A, Atmel.AVR.V3.20A, CR16C.V2.10A, H8.V1.53I, MCS-51.V6.10A, Mitsubishi.740.V2.16A, Mitsubishi.M32C.V2.11A, MSP430.V3.20A, NEC.V850
  129. how to force DC to use a specific cell ?
  130. Problem with Nios Development Board (Cyclone)
  131. Data Swtich from LPT to LCD Module!
  132. the compactflash true ide mode access
  133. SRAM to be able to Read/Write SDRAM
  134. Jtag problem for Virtex II pro (XC2VP20-6FF896C).
  135. Silly Xilinx Foundation question...
  136. Epp interface with Cyclone
  137. USB2.0
  138. Question abut ISE
  139. IO Timing constraints with internal clocks
  140. Clock loading in XC9572 CPLD
  141. how to get SDF file from netlist
  142. minimum module name length in 6.3i?
  143. chipscope pro problem (par)
  144. Number of FPGA users?
  145. Xilinx EDK PLB/OPB bridge (and IPIF)
  146. Spartan3 Engineering Sample Performance?
  147. Problem including header files in a C/C++ project using Altera's Nios II IDE
  148. need an fpga board
  149. SRL16E_1 primitive instantiation in VHDL
  150. comparator problem
  151. XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
  152. Need Virtex 2 Proto Board
  153. FPGA Board Newsletter, November 2004
  154. Physical Compiler Vs Design Complier
  155. hostid for Actel Designer
  156. FPGA for Game and Amusement
  157. Xilinx Maximum output required time after clock
  158. FPGA Advantage and Xilinx Specific Libs (like Unisim)
  159. ise and edk integration
  160. FPGA/CPLD Basics
  161. XST - Memory Problems
  162. FPGA configuration download - How is it done?
  163. FPGA : configuration
  164. How to preserve net names in DC while synthesis
  165. [Ad] FPGAWorld has teamed with Demos on Demand™
  166. FPGA & DDR-SDRAM
  167. TIME borrowing in synthesis
  168. Xilinx Spartan 3 CoreGen Counters
  169. SysGnen 6.2: problem with DDS module
  170. "frying" FPGAs
  171. compactflash interface problem
  172. Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
  173. Using Xilinx fpga pins on external connector
  174. max frequency with TSMC .18u std cell library
  175. In ISE 6.2i, CoreGen doesn't show any component?
  176. fpga: 4 Millions Domains data with Category
  177. [Ad] FPGA Boards Massive Sale
  178. Board-level clock phase delay calculation in the fpga board?
  179. Webpack / Multisim - jitter simulation ??
  180. XST: suppressing incorrect optimizations in VHDL code
  181. explicitly define latch to avoid WARNING in xilinx webpack?
  182. Altera Quartus 4.0 - inconsistent simulation results
  183. CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
  184. Do you know this board?
  185. dw_prefer_mc_inside command in DC
  186. Xilinx V-II BUFGMUX oddities..
  187. Random number generation in testbench
  188. xilinx edk 6.3
  189. Xilinx Platform Studio- I don't get C source code error messages.
  190. clk warning
  191. spartan-3 development board
  192. information about Nuhorizon Spartan-3 Development Board ?
  193. synthesizeble Wait Statement in Procedure
  194. OPB versus PLB
  195. Question to TBUS-Placement in SPARTAN3 again!
  196. Strange XST error in ISE 6.3.02i
  197. Newbie: Read from Compact Flash using System ACE
  198. Looking for an archive of QuartusII v2.0 (yes v2.0) to download
  199. SysGen 6.2: Error when generating hardware cosim
  200. JTAG Configuration
  201. SPARC V8 SoC in FPGA? Its already cost effective!
  202. JTAG Registers
  203. OPB in Verilog
  204. Help on Quartus Megafunction on Dual Port RAM sought...
  205. JTAG Configuration
  206. Using Sync Reset as Async Reset
  207. inefficient mux synthesis in quartus
  208. ModelSim Directory
  209. Clock Extraction from Bi-Phase Data
  210. Best Place and Route
  211. PCBs for modern FPGAs.
  212. Altium board again
  213. Bus interfaces & FSMs
  214. Viewing/Controling C-Build Outputs
  215. Programmable I/O Card for the PC - does it exist ?
  216. PLL Clocks on Cyclone Devices
  217. ISE and Clocks
  218. FPGA board checking
  219. initializing custom memory with .mif (or .hex) in Quartus 3
  220. Low-power FPGAs?
  221. ISE Mapping problem
  222. Virtex-II Pro DDR Memory Controller
  223. SCSI
  224. PacoBlaze 1.3b
  225. Hello Xilinx folks -- please answer
  226. Q: configuring FPGA Spartan2
  227. System Generator problem with XtremeDSP
  228. VCXO Emulation
  229. Altera NIOS2 flash prgrm port
  230. Xilinx and Altera Modelsim on the same PC?
  231. Looking for FPGA design services in India or similar
  232. Spartan 3 - Internal busses & tristate ?
  233. Altera Cubic Cyclonium
  234. Verilog Simulation problem
  235. VxWorks: Java
  236. CoreConnect Bus : How to speed up the PLB
  237. cyclone config problem in my board
  238. ModelSim is ungraceful with my stupidity...
  239. lpm_counter instantiated in VHDL has a glitch
  240. Re: Free *** hotline from China
  241. strange behavior in lpm_counter
  242. Assembler for PicoBlaze in Perl
  243. Nios & off-chip memory
  244. Small survey for Handel-C writer
  245. Xilinx translate error : Cannot find signal "clk"
  246. interfacing a PC based program with a FPGA
  247. Partial reconfiguration of Xilinx
  248. Webpack 6.3i support for Spartan 3
  249. When will the ML401 source be released?
  250. Async reset