PDA

View Full Version : FPGA


Pages : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 [76] 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

  1. Graphic LCD
  2. Nios performance
  3. synthesizable vhdl coding style
  4. nios2 flash programmer
  5. Any suggestion for an IP project
  6. Altera support getting worse and worse......
  7. Sierra ic .com
  8. Issues with a batch of Virtex-II chips
  9. test
  10. edk and xilinx multimedia board
  11. Xilinx: Pitfalls of chaining DLLs
  12. Using c++ with xilinx EDK tools
  13. RocketIO swift simulation under VCS
  14. EDK, XST & inouts
  15. Is Altera Cyclone a good choice ?
  16. Shift register example?
  17. Question about microblaze C complier
  18. CRC-4 algorithm using in G.704(&G.706)
  19. eda software
  20. microblaze with opb, brams?
  21. Printing in ChipScope
  22. Virtex4: Usign OSERDES + LVDS Deserializers
  23. Make program stop
  24. PPC 405 in Virtex 2 Pro 30-Turning off "Critical-word first" loads
  25. ModelSim Timing Strategy
  26. Confluence 0.10.3 Released
  27. FPGA Hardware/Cell Diagnostics
  28. IOBs in virtex4?
  29. Simple counter
  30. Cool File Encryption Software Released.
  31. 3.3V device programmable with 5V?
  32. thread programming support in EDK?
  33. binary constant divider theory
  34. VGA core
  35. DNL and INL calculation
  36. clock split approach for 270MHz design in Spartan2E
  37. Efficient Voltage Regulators Spartan 3 Current Requirements
  38. PPC405 sleep?
  39. Xilinx RPM in Makefile?
  40. FPGA programming newbie
  41. Virtex4: On using a LC clock pin for global clock.
  42. PLB
  43. Electronics on ... www.etantonio.it
  44. .rbt file question
  45. How to use file input output function?
  46. Protecting IP in China
  47. Questions about multiple rom instances in Quartus II
  48. How to display synplify_pro version in tcl command
  49. Avnet Spartan 3 Evaluation Board and PCI
  50. SPI serial output counter or latch?
  51. OPB IPIF HELP!!!
  52. Xilinx Post Place and Route FIFO problems
  53. Any Altera FIFO not a power of 2?
  54. Xilinx Spartan 3 kit - VHDL design question
  55. wireload model./custom wl creation
  56. ATM Cell Payload Scrambler / Descrambler Process Explaination Required
  57. ISE:ERROR:Xst:829: Constant Value expected for Generic 'U'?
  58. Question about Virtex II Pro - Partial Reconfiguration
  59. Cyclone clock
  60. Recommended Single Board FPGA manufacturer
  61. Updated Stratix II Power Specs & Explanation
  62. Strange clock problem with Synthesized netlist in Quartus
  63. opencore under edk 6.3i
  64. Weird Mircroblaze programm execution
  65. clock division / multiplication in xilinx cpld
  66. Xilinx Spartan 3 kit - displaying unique numbers
  67. Re: Using the 7 segment displays on Xilinx Spartan 3 kit
  68. Using the 7 segment displays on Xilinx Spartan 3 kit
  69. IPIF
  70. Xilinx BRAM FIFO problems ModelSim Post Place and Route
  71. OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
  72. Fast counting in Spartan 3
  73. Programmable clock problem
  74. Announcing Samplify for Windows: high-speed sampled data compression
  75. Xilinx : UCF
  76. 2 microblaze access same BRAM ?
  77. xilinx MGT compatibility?
  78. Why are the NIOS toolchain sources removed from Altera's ftp?
  79. ISE and IEEE.Fixed_pkg (fixed point math for synth?)
  80. Altera's Megafunction altaccumulator
  81. ISE versus Modelsim inconsistency and attribute definition
  82. doubt on configuring FPGA
  83. RocketIO in 32-bit Mode
  84. configuration problem xc2v6000/8000
  85. Variable phase shift on Spartan3 DCMs. Does it work?
  86. Sending text from fpga to printer
  87. C program to big for microblaze?
  88. NIOS - newbie
  89. XMD/GBD problems
  90. GEMAC and MGT on ML300
  91. Problem with JBits 3.0 Tutorial
  92. ROM inference in Spartan3
  93. FPGA design problem
  94. FPGA synthesis problems
  95. Virtual Pins in QuartusII
  96. Writing IP-Cores while sleeping ;)
  97. Basics of BFM
  98. Flash problem
  99. Newbie : Xilinx Ml310 platform
  100. HELP: Graphic LCD + Keypad + printer
  101. theta(jb) for V2-PRO in FG676
  102. See the next high-wire act, this time on power consumption
  103. In need of some life-changing advice
  104. newbie question
  105. second flop in asyn reset distribution
  106. Newbie: add opb_ddr to a project
  107. Plea for help with MAX7000S
  108. Local clocking in spartan 3
  109. Global clock as input of a FF
  110. ASIC vs DSP vs FPGA
  111. ProAsic3 (PA3)
  112. Learning resources for Xilinx memory controllers
  113. Beginner question: How to interface ram an Memec Spartan IIE - Board
  114. quartus - Linux or Windows
  115. laptop for fpga design - acer ferrari?
  116. newbie : IP cores
  117. Resetting FIFO
  118. Beginner: running EDK 6.3 in linux
  119. .vho (Xilinx Core Generator) to .vhd ??
  120. virtex4 distributed RAM
  121. quartus "make clean" ?
  122. vxWorks soft boot with ML310/ VirtexIIPro
  123. BRAM utilization - how to calculate
  124. Input Timing Specification
  125. Microblaze and Picoblaze
  126. BFM Basics
  127. V4LX25-ES and systemACE
  128. Retaining not used nodes
  129. SimmStick FPGA module
  130. System Generator: does it support high-level programming?
  131. SATA and RocketIO
  132. FPGA Prototyping
  133. Max. Operating Frequency - Timing report
  134. Anyone want a free iPod?
  135. MAP problem
  136. opb_ddr connection to DDR chips
  137. usb 2.0 micromodule
  138. comp.arch.fpga : Generate libraries and BSP`s
  139. Mixed Language synthese Microblaze
  140. xilinx parallel cable IV
  141. WARNING:Xst:382 - Why so many?
  142. Impact with Linux Kernel 2.6.x
  143. Virtex4: where is ICAP?
  144. xilkernel and threads
  145. Cyclone configuration device
  146. Xilinx makes dreams true :)
  147. Quartus project files
  148. Quality of Xilinx ML401 video output?
  149. GND and VCC pins
  150. ISE6.x/iMPACT, JTAG fails after any completed command
  151. problem with xilinx platform studio 6.2i
  152. warning messages,NgdBuild:454,DesignRules:331
  153. How to fix this synthese warnings?
  154. Debug module and bufg in Xilinx EDK
  155. error in xst
  156. Digilent JTAG cable parallel port pinout (Spartan 3)
  157. Altera's NIOS2 examples...
  158. OPB ZBT
  159. Coprocessor "Standalone"
  160. EDK+IPIF: Customizing wizard result
  161. new MicroBlaze uClinux build platform anybody having full success ?
  162. vieux livres
  163. ambiguous number of BLOCK RAM in SPARTAN3
  164. This Is My Task - Have A Look
  165. Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
  166. memory size of C code
  167. Multi-Master problem with OPB
  168. VoIP on XESS XSB
  169. Spartan-3 Starter Kit supplier in the UK?
  170. PPC on Virtex2P: Jumpstart, recommended reading?
  171. C compiler for Picoblaze
  172. help "bank does not exist"
  173. Beginner : problem in Xilinx Platform Studio with selection of board names
  174. Altera, QuartusII and internal tristates
  175. How to locate a net in the design
  176. NIOS2 toolchain rebuild...
  177. I have a problem with Excalibur Stripe Simulator(ESS)
  178. Xilinx Virtex4 / Spartan3 High Speed Designs
  179. EDK + user ip : can't find library
  180. Finding DDR SDRAM SODIMM(200 pin) socket.
  181. RoseRT + Threadx + Xilinx Microblaze
  182. CLOCK_SIGNAL constraint/XST?
  183. Help on a FPGA design
  184. Help on a FPGA design
  185. Help, i'm geting warnings :-(
  186. PACE error
  187. gdb-stib and microblaze
  188. Q, compile option, mb-gcc
  189. problem with Modelsim 5.8 Xilinx Edition
  190. How to handle clock skew?
  191. Source of reset for synchronous reset can lead to metastability?
  192. Altera PLL and Timing Analysis
  193. EDK IPIF Wizard : How to get started?
  194. Spartan-3 Static Timing Analysis with Voltage/Temperature Pro-rating
  195. Trouble with XilinxCoreLib\vhdl_analyze_order
  196. Altera FLEX 8000
  197. Modifying a post PAR xilinx design
  198. xil_malloc vs malloc
  199. Constraint on a asynchronous signal
  200. Virtex II Slice Design - ARGH!
  201. MP3 Player Project
  202. Using FPGA Compiler2 with coreConultant?
  203. Synplicity and Mentor denying evaluation licenses
  204. Asynchronous Inputs Question
  205. reading from CF card
  206. Pericom PI6C2404 equivalent
  207. Model Sim: Color Printing
  208. Synchronizing multibit bus - 2
  209. gate/xilinx slice
  210. 100Mbps ethernet core
  211. Input logic level on Spartan 3?
  212. Oscillator for Digilent Spartan 3 Starter Kit
  213. Evaluating EDIF netlist
  214. Synchronizing multibit bus
  215. Init of BRAMs with ISE flow.
  216. Co design : Verilog and C : Examples needed
  217. Metastability MTBF in Cyclone
  218. Any solution for solving setup or hold time violation?
  219. Temat:Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
  220. Active HIGH / Active LOW
  221. FPGA configration Data/Firmware
  222. Asynchronous Inputs Question
  223. Init of BRAMs with ISE flow.
  224. IPIF
  225. Listing unrouted nets in FPGA Editor
  226. quartus hierarchy strangeness
  227. Xilinx Virtex2p configuration
  228. which version PCI LogiCore for XC4000E?
  229. Lattice LFEC20
  230. EDK 6.2 Synthese Error
  231. Master Serial Programming
  232. OPB IPIF user register interface
  233. changing directory location
  234. Master Serial Programming
  235. could I drive Altera MAX II CPLD with LSTTL outputs?
  236. spartan3 starter kit now comes with eval version of edk
  237. FPGAs used to crack RFID crypto
  238. OT: Design security
  239. Actel A54SX72A - FF with clear and preset? Necessary for tripleredundant register
  240. which version PCI LogiCore for XC4000E?
  241. Re: Trouble with Post-Place Simulation
  242. i need xilinx edk
  243. material finding, edk on Linux
  244. Attempts to run Quartus Web Edition in linux (wine)
  245. Altera subscriptions deleted?
  246. How to change the font in EDK's text editor?
  247. Quartus II megafunction
  248. Sensitive List Question
  249. Altera Quartus 4.2 Service Pack 1 fails to install
  250. New code FLASH memory