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  1. Lattice's XP (flash + sram) fpga
  2. RS232 VHDL-core
  3. [ANN] jjtag - Java JTAG interface
  4. Global Reset paths
  5. Differences among the FPGA development tools.
  6. NIOS SRAM Problem with Stratix
  7. Call for Papers: 2005 MAPLD International Conference
  8. SPROM for Spartan II
  9. Using BUFG with internally generated clocks
  10. dsbram memory addressing
  11. Basic cheap fpga configuration
  12. Async FIFO problem...
  13. ISE Foundation/Ba*** 7.1i evaluation for Linux
  14. Xilinx vs Altera high-end solutions
  15. Altera vs Xilinx choices for high end designs
  16. Good, affordable verilog simulator
  17. Trace length from FPGA to USB PHY
  18. RPM creation
  19. malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
  20. Guideline for PCB routing for PCI signal
  21. File I/O with Synplify
  22. What's the Altera Equivalent of a Xilinx .rbt file?
  23. ML310 boot settings
  24. EDK service packs?
  25. Version mismatch ?
  26. NIOS2 1.1 toolchain sources...
  27. Hierarchical Synchronous Design
  28. Surge in S2? ~3 amperes at cold for a millisecond
  29. Great site for computer hardware
  30. Asynchronous processor !?!
  31. Xilinx / Altera TCLK termination (Pull up or down)
  32. Readback
  33. Cheap alternatives to Mach 210s
  34. VoIP & FPGA
  35. using NET1 external module with a Spartan-3 board
  36. EST Guide
  37. adding SDRAM to the S3 starter kit
  38. DCT in FPGA
  39. State Machine Trouble
  40. Spartan 3 - insurge current
  41. [ICCIMA'05] Final Call for Papers; Due Date March 10, 2005
  42. [ICSEng'05] Final CFP - due date March 10, 2005
  43. Help with 22v10 and WinCupl :(
  44. spart 3 uart example
  45. reading data from register and writing to ram
  46. SRAM on spartan3 board
  47. spartan 3 design projects
  48. XST block ram init in include files
  49. for debugging
  50. simulation and real world
  51. Synthesis with EDK 6.3
  52. using atmel fit2500 fitter for a atf750
  53. Q: state encoding in FSM for simple cases ?
  54. Planning to Build Complex Wireless SoC...Anybody interested??
  55. Tristate problem
  56. Regarding Linux on ML 310
  57. intermittent sysACE hang on ML310
  58. problem using Modelsim Mxe3
  59. Newby Getting started with FPGA
  60. RAM Address Calculating
  61. 1,5Mhz Clock
  62. VHDL Instantiation
  63. How to profile performances of an OPB bus
  64. Displays an image in the XS Board RAM on a VGA monitor
  65. Xilinx/Howard Johnson's crosstalk web seminar
  66. test
  67. xilinx xpower - frequency estimation of internal nodes
  68. Jitter calculation for RocketIO reference clock
  69. ISE guide mode broken?
  70. How to readback a BRAM
  71. making an fpga hot - addendum
  72. XC9572 64 pin VQFP package
  73. How to read back!
  74. Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
  75. where to get Xilinx Driver API document?help!
  76. HELP!!! Interfacing Virtex-4 FPGA with SDR SDRAM
  77. PLB IPIF + Master + DMA
  78. IBUFG as ? component
  79. bad synchronous description error
  80. programming ATF750 in ABEL
  81. newbie ABEL questions
  82. Xilinx ML310 board's IO
  83. Genlock
  84. EDK evaluation version with Spartan 3 board arrived today
  85. timing diagram tool linux
  86. Senior Digital Design Engineer
  87. Design Compiler and Xilinx-Libs - Possible ?
  88. Yet another SDRAM design :)
  89. sysACE load vs bootloader load of vxWorks on ML310
  90. [Promo] Danville releases SHARC kit for $199
  91. Fault Tolerant FPGA design
  92. FPGA / DSP - Urgent need in Orange County, CA
  93. spartan3 development board in Europe?
  94. spartan3E price
  95. PLL code
  96. Altera APEX20KE clock problem
  97. Need suggestion abt FFs without RST for pipelined datapath.
  98. Lattice lowcost flash FPGAs announced
  99. Timing Error large enough to cause problems?
  100. Suppressing extra XST messages
  101. Pci
  102. Xilinx ISE7.1
  103. Xilinx ISE history?
  104. Spartan3E
  105. Spartan-3E and SPI Flash bootstrap
  106. Error on launch the Simulator
  107. Frustration on Xilinx Device Drivers API
  108. RocketIO minimum bitrate and other questions
  109. Nios II timing question
  110. MGT RXLOSSOFSYNC problem
  111. Help with XST warnings (2)
  112. Resetting Virtex II BlockRAM
  113. Part of a ranged signal
  114. Examples with GEMAC and ML300 board?
  115. pin assignment on an expansion module
  116. Xilinx *.rbt file into AMD flash
  117. Memory or registers and JTAG
  118. SR latches in Xilinx devices?
  119. Has anyone tried the "LogicPort" 34 channel 500MHz logic analyzer?
  120. SoC positions in Bangalore
  121. FIFO Problem
  122. 1
  123. Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
  124. virtex4 virtex-4 FX eval board
  125. FPGA interface to an asynchronous microcontroller memory bus
  126. FPGA tool benchmarks on Linux systems
  127. high fan out skew in v2pro
  128. modelling Bi-directional address/data multiplexed bus
  129. RocketIO, where to start?
  130. OT: funny idea
  131. packages(2)
  132. Missing Virtex4 Speedfile
  133. synthesis tool for systemc
  134. SystemC to Verilog Translator v0.4
  135. Update EDK 6.1 to EDK 6.3
  136. Problem with LXT970A
  137. Planning to develop wireless chip(need to build a team)
  138. Quartus 4.2 SP1 woes with Samba & [email protected]#$ "Flex"LM
  139. maximum freq of operation of a circuit
  140. maximum frequency of operation
  141. Resource (FMAPs) use when using block RAMs
  142. FBI Alert - Computer Virus
  143. I2C protocol to communicate between FPGAs
  144. Platform Cable USB
  145. The third high-wire act: Signal Integrity or "It's the inductance, stupid".
  146. PLB Retry (Rearbitrate ) Request from PLB DDR Slave Controller
  147. block adder for Altera!
  148. programming 2 pulses using VHDL
  149. setup-hold time problems
  150. livedesign or ise
  151. lwip on spartan3
  152. spartan 3 vs virtex 2
  153. Interfacing virtex 2 pro to flash memory
  154. EDK IPIF FIFO Problems
  155. pci x core on virtex II
  156. SVF file
  157. Maximum Current utilized by Spartan-3
  158. SD Card question?
  159. Error in ISE 6.3
  160. dealing with NGO files
  161. Virtex-4 performance, where is it?
  162. Can't create Bus-Tap in Xilinx' ECS
  163. Virtex4 : speed improvement
  164. IP unnecessarily using Spartan-3 DCM?
  165. VIE in electronic and FPGA design
  166. EC/ECP Map Problem
  167. Engineer in Eastern Europe
  168. Ml310(xc2vp30) with ppc 405,multi processor share memory?
  169. Digilent D2SB FPGA Boards
  170. Questions on XPower: "Confidence level is shown as inaccurate"
  171. Synthesis question
  172. Using XBERT(XAPP661) with EDK6.3SP1
  173. publishing IP
  174. Altera available from Digikey
  175. pld macrocell usage
  176. Fast 28x28 multiplier + adder in Virtex4
  177. Problems with XPower
  178. NiosII Vs MicroBlaze
  179. edk, chipscope_icon and chipscope_ila
  180. Implementing Multi-Processor Systemsin FPGAs
  181. Synchronous design
  182. Prescalable counter
  183. Adjustment for FPGA-FAQ 0044
  184. Multiple addition(2)
  185. Multiple additions
  186. FSL : only reads 16 times
  187. Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
  188. routing delays (Xilinx)
  189. How to synthesize the xilinx ip core?
  190. Memory Controller Operation
  191. cheapest CPLD
  192. "DSP Dev kit stratix II edition" Vs "ML401 Evaluation platform"
  193. generic
  194. embedded 2005 in Nuernburg
  195. Constant Functions in Modelsim
  196. The real performance leader: V4
  197. Signal Integrity break-through: V4 packaging
  198. Frustrated with Altera
  199. FPGA : file generation
  200. Spartan-3 partial reconfiguration trouble
  201. Altera JTAG Jam STAPL player portet to Linux for Byteblaster?
  202. XST: How to select the architecture for synthesis?
  203. what's the difference between syn FIFO and asyn FIFO?
  204. Quartus DESIGN ASSISTANT tool
  205. what is the matter?
  206. Problems with a 4-MicroBlaze Multiprocessor Architecture
  207. interrupt handler problem
  208. Virtex-4 FPGA with Jbits3.0?
  209. re:Debugging error in VHDL
  210. reading from CF
  211. Debugging error in VHDL
  212. CfP Concurrent Process Architectures 2005
  213. FPGA board with best cost/CLB ratio?
  214. INTO FREE COMPUTER GEAR? FREE SAMSUNG 17" LCD Monitor NO TRICKS-NO SCAM-NO PURCHASE!
  215. Is there any compatibility difference between The parallel JTAG PC4 and JTAG III??
  216. Frequence max: many question from a beginner
  217. XilKernel Problem on Spartan3 Board
  218. SD Card and FPGA
  219. accessing external RAM on Spartan3 starter board
  220. Tristate Discussion
  221. Pin Declaration in new EC/ECP FPGAs
  222. USB 1.1 core
  223. virtex II register file
  224. Spartan3 Power Supply Circuits
  225. Exporting Modelsim Values?????
  226. Jitter and Static Timing Analysis
  227. cyclone's pll
  228. Hardcopy Vs ASIC
  229. Reconfigure your dreams: fully reconfigurable computer in DIP40 !
  230. EDK6.3i Memory conflict.....
  231. Sending information between VHDL modules from the top level module
  232. downloading program to external ram
  233. WYSIWYG option in xilinx webpack 6.3
  234. DSP56651/DSP56670 - Motorola RAM-based emulation devices
  235. does anyone have a c compiler for the picoblaze
  236. SRAM & Flash Address Bus w/EMC
  237. JOP VHDL simulation
  238. BACK to FPGA
  239. difficult to build counter, some help please : (
  240. Xilinx Memory Interface Generator
  241. why are PCI-based FPGA cards so expensive ?
  242. beginner: running linux on xilinx ml310
  243. Help using the ML310 developement board
  244. VHDL State Machine - Literature
  245. hdl:lament
  246. why to use FIFO on FPGA?
  247. Antti Lukats: all my past live projects to be published...
  248. EMC and Shared SRAM/FLASH Bus
  249. having EDK and microblaze
  250. distributed shared memory in fpga?