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  1. Xilinx multiplier out of slices
  2. Virtex 4 Power consumption
  3. Re: What is the cause of a "can not see clock" problem in logic analyser?
  4. A PC for make synthesis
  5. OCM interface to SDRAM
  6. Virtex-4 Routing
  7. Speed acceleration !!!
  8. Writing to Ram
  9. ispTRACY-Lattice vs. SignalTap-Altera
  10. Timing Reports Xilinx.....Max. freq of operation?
  11. Looking for a RocketIO expert in Ottawa, ON
  12. JTAG and SPROM for Spartan II-e
  13. PPCs sharing an OCM BRAM
  14. Xilinx Impact in Linux 2.6.x
  15. And gate in Neural Network
  16. HDL in safety critical applications
  17. low budget SystemC to VHDL Compiler?
  18. FIFO as a Logic Analyzer; Clock synthesizer
  19. Xilinx ISE Warning: FF/Latch <> is unconnected in block <>
  20. parts needed: XC4VLX40-10FF668CES
  21. Is Cyclone-2 EP2C5 or EP2C8 available? If not, when?
  22. Do Synplify DSP and Accelchip support multiple clock domains?
  23. xilinx ml310 + linux + System.map file problem
  24. Simulation in modelsim.... Multiple Drivers.......
  25. VHDL or Verilog
  26. CAM for FPGA ...
  27. ATA FPGA IP Core
  28. LVDS pin assignment
  29. Power Estimation without Pad Connection (XPower)
  30. AHDL and quartus II simulation
  31. Virtex II Scrubbing, Readback and Reconfiguration time durations
  32. Bug in DDR template in Lattice FPGAs ?
  33. Unconstrained ports for synthesis
  34. And gate in Neural Network
  35. Ambigous operator '&'
  36. Cost of Altera DSP Builder
  37. avnet dev. kit flash reprogram
  38. Some signals became ? and missing on the simvision, why?
  39. College Project
  40. Recover back up
  41. OV6620 PCLK CLK
  42. Perl Preprocessor for HDL
  43. actel blockram the easy way?
  44. Linux, ISE 7.1, problems, problems, problems ....
  45. UCF File - How to define this Constraint?
  46. What is the cause of a "can not see clock" problem in logic analyser?
  47. Strange FPGA problem
  48. Celoxica RC1000: problems accessing fpga control registers
  49. How do I convert binary data from Agilent logic analyzer 16702 into plain text?
  50. Spartan 3E availability
  51. Can't find folder
  52. source control and Xilinx ISE 6 and 7
  53. Test
  54. Test
  55. Problem installing ISE 7.1
  56. [Info]Platform USB.
  57. OPB to Wishbone Wrapper
  58. Declining a job offer
  59. DSP-PC architectural advice needed.
  60. Tutorial on FPGAs
  61. Missing post
  62. combining two EDF netlist in ISE
  63. Altera logic programmer card
  64. Odd Oversampling
  65. debugging source code for PowerPC
  66. Multi-page schematics (.bdf) in Quartus II?
  67. SPROM JTAG confusion!
  68. Microblaze Functions (Xilinx Specific)
  69. MAX7000S CPLD tri-state OE delay
  70. FPGA/Embedded courses online or near Toronto
  71. Spartan 3E slower that Spartan 3?
  72. The DLP from Texas Instruments...
  73. EDK: microblaze local memory
  74. rocketio decoupling
  75. Power supply design
  76. Help OPB <> Wishbone wrapper
  77. FPGA Design Introduction
  78. Differential timing specification in Xilinx FPGA
  79. Xilinx tools on Linux
  80. hdl designer cvs in remote repository
  81. Technical Journals on FPGAs
  82. ISE 7.1 GUI (slightly OT)
  83. EDK:input to microblaze
  84. Hobby or job? (FPGA User's groups anyone?)
  85. salary ballpark please guys
  86. increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)
  87. DCI question
  88. sharing a common resource... potential problems...
  89. Functional vs, Timing
  90. different I/O buffers available inXilinx FPGA
  91. ISE Testbench/Schematic Generation ignores package
  92. Soft CPU vs Hard CPU's
  93. clock input over an I/O pin
  94. Help OPB <> Wishbone wrapper
  95. free-ip
  96. Internal clk gen on IO PAD in Xilinx FPGA
  97. ANN: USB/FPGA board with programmer's interface
  98. Xilinx TMRTool price
  99. Connecting Virtex2pro to Virtex4 via RocketIO MGT's
  100. Fitting functionality in an XC2VP30 FPGA.
  101. tools used for ASIC synthesis
  102. Verilog problems with SelectRAM clocking within a finite state machine
  103. Altera DSP dev board stratix II
  104. Free VHDL Analysis Tool (vhdlarch 0.1.0)
  105. Flowcharts and diagrams
  106. "The ISE 7.1 Experience"
  107. PPC405 Performance Monitoring
  108. Embedded MicroBlaze solution
  109. Xilinx VIIPro power supplies
  110. help neeeded for byteblaster of altera
  111. Reading old F2.1i schematics
  112. LUT in fpga
  113. Timing and synthesis problem+xilinx
  114. virtex4 reconfiguration time
  115. Regarding driving of SCL and SDA pins of I2C
  116. Simulation and actual FPGA implementation, how different it is?
  117. opb_ethernet timing constraints
  118. RLOC question
  119. MIMO Channel Estimation WCDMA
  120. Error synthesizing two Xilinx MacFir core
  121. Quartus POWER_UP_LEVEL bug?
  122. General question about soft CPUs
  123. 5V PCI interface
  124. Ethnet samples using EDK??
  125. Ethnet samples using EDK??
  126. Global buffer feeding non clock pins in VIRTEX II
  127. 2 bit multiplier
  128. How do I disable Microblaze on-chip hw debug
  129. Import user Core with a Tri-state Port to EDK
  130. question using xapp333
  131. Xilinx PCI Express solution with PX1011A PHY any closer info available?
  132. Xilinx VirtexII master serial mode problem(cclk)
  133. Xilinx 7.1 ISE patch - for XC9500/XL/XV and CoolRunnerXPLA3
  134. Verilog examples???
  135. process trouble, error: multi source
  136. PLB IPIF on Virtex 2 Pro
  137. xilinx virtex 4 download cable
  138. State of MAX7000S I/O pins before programming
  139. lcd controller - how to realize it?
  140. Timing
  141. DC component removal in FPGA
  142. Application using coprocessor interface
  143. free HDL ebook?
  144. Xilinx Platform Studio - Vertex II Pro board
  145. Altera and VHDL library
  146. XMD only operating in compatibility mode under Suse9.2 pro
  147. CCD and Graphics - which FPGA?
  148. easyfpga is not easy
  149. xapp134 on sdram controllers: @ bits reordering?
  150. Shared bus on FPGA
  151. Problem with appnote XAPP622 (SDR LVDS)
  152. LVDS for lcd panel and RocketIO
  153. vhdl code for the 2-line lcd on xilinx boards
  154. implement the JTAG MASTER --ACT8990 by using FPGA
  155. edk annual renewal cost?
  156. vhdl and clock-pin
  157. Question about Xilinx OPB/PCI bridge
  158. clk_div illigal connection
  159. A PCI FPGA card I found on ebay
  160. Spartan-3E based board available now? or is Memec advertizing vaporware ?
  161. ISE 7.1 won't play with EDK 6.3 ????
  162. Neural Networks in FPGA
  163. EDK: Microblaze with XMdstub
  164. where can i get xilinx ise 7.1 evalution ?
  165. How to debug with XMD
  166. ISE 7.1 for 64 bit Linux ???
  167. ise 7.1 sp1 BEWARE !
  168. ISE/Impact 7.1 Linux Driver problems
  169. rules to assign pins to FPGA?
  170. Getting started with Virtex-II Pro LC Dev Board
  171. ML310 xirtex II pro development board: HOW TO WRITE onto the DDR DIMM?
  172. XST -vlgincdir
  173. Altera programming via Embedded processor
  174. PicoBlaze JTAG Program Loader problems
  175. Simualtion of Rocket I/O MGT in ModelSim XE
  176. Heatsinks with fan for Xilinx FF1152 on PCI card
  177. DLL feedback delay
  178. DCT
  179. running microblaze from bram through OPB-bus
  180. FPGA Configuration Simulation
  181. Difference between BUFGDS and IBUFDS on clocks
  182. Linux VHDL Simulator
  183. Clock Jitter on Xilinx FPGA
  184. FPGA Layout question
  185. xilinx embedded MAC
  186. ADPCM IP core
  187. Interesting article about Xilinx FPGAs in the new Cray
  188. Slow rising strobe used to clock IOB's, can it cause trouble?
  189. Major Adresses on Xilinx Virtex-II
  190. 8 pit PWM generator in one Xilinx Slice !
  191. Sdram controller on the Altera Cyclone board!
  192. xilinx appnote 636
  193. Hey Xilinx
  194. Xilinx ISE 7.1i / stuck down XCR3064 outputs
  195. Re: LVDS PCI card is needed
  196. LVDS PCI card is needed
  197. Modelsim simulations without ISE
  198. Single Event Functional Interrupts (SEFI) in Virtex
  199. How to use the library in VHDL (ISE)?
  200. Xilinx ISE Input Pins Problem
  201. VHDL to schematic conversion
  202. A "simple" problem...
  203. HWICAP BRAM access (with EDK)
  204. Spartan II/E Configuration readback
  205. CPLD: collapse
  206. Xilinx V2-Pro + Select Map programming
  207. FPGA with 2 JTAG ports
  208. EDK-Creating new peripheral
  209. 80x86 verilog (not complete!) sources released
  210. ISE 7.1 unisims and cver simulation
  211. ISA vs. patent/trademark
  212. Book?
  213. ucf timing constraint question
  214. Protection measurements
  215. Quartus 5
  216. DCM LOCKED as reset
  217. WebPack_7.1 on Linux ?
  218. Structural vs Behavioral
  219. Re: can c++ code be loaded to a hardware PGA coprocessor card
  220. Stupid question
  221. Need Help
  222. Reverse engineering ASIC into FPGA
  223. IBUFG and BUFG +xilinx
  224. Xilinx XPower - Accuracy Information
  225. ML310 z-dok connectors
  226. Last rites declaration of Ioannes Paulus PP. II (Karol Wojtyla)
  227. how to use both FFs in a CLB's slice using LOC or RLOC
  228. XC95108 problem
  229. PLX-9656 Controller interface
  230. XMD : Running XMD with Caches on
  231. EDK:Question regarding opb_uart
  232. USB blaster
  233. Open PowerPC Core?
  234. IPIF Signals
  235. RAMB16_S9
  236. Question regarding EDK
  237. Question regarding EDK
  238. Question regarding EDK
  239. 10 Compelling Reasons USANA Should be Your Opportunity of Choice
  240. Xbox , chip mod & CPLD
  241. [info] Sine generation
  242. ModelSim XE and WindowsXP
  243. OPB Master
  244. DPSK Receiver in Vertex-4
  245. fpga async design help me
  246. Parallelsignal at 85 MHz
  247. RAM Synthesized away
  248. 4/1
  249. ABEL alias names
  250. Transputer delivery