- Why do VHDL gate level models simulate slower than verilog
- where are the PAO files for the system.bsp stored???
- XPS: Create/Import File structure
- Problems with Constraints (Xilinx, ISE 6.3)
- DDR2 based Xilinx Development boards ?
- Q, BRAM initializing using INIT_0X
- For accessing my SDRAM,what should i do?
- Linux on Xilinx ml310
- CORDIC bit-serial vs. bit-parallel
- Xilinx IP: PCI Express
- Detaching the schematic viewer under ISE Webpack
- VHDL array question
- About back annotated simulations...
- Which Simulators
- Jam Byte-Code Player for 8051
- Virtex 4 MGTVREF pin reference circuit
- open support question to Xilinx. should be fairly simple to answer.
- Virtex-2 JTAG problem
- Help needed!!interrupt handling in microblaze system
- delays
- edk sram interface - board definitions files xbd
- Registers replication on Xilinx IOBs
- Is a gated oscillator using NAND okay within a Cyclone FPGA?
- Bullshit Achieves Literary Status
- Silicon Valley FPGA position
- Altera Apex20KE PLL output jitter problem
- why is it wrong with "sin"?
- Xilinx : Clock Swallowing
- SPI interface cpol & cpha
- wide ROM
- Microblaze interrupt problem
- Universal logic modules vs NAND-like modules
- Serial communication
- FPGA design under Mac OS X ?
- Quartus II Fitter Problem
- Virtex-II Switch Matrix Performance
- floorplanning
- microblaze and 64 bit memory over PLB bus
- Whats going on here?
- Handling Interrupt
- Tristate-Master-Slave testbench description
- PowerPC and application in external RAM
- Q)BRAM VHDL simulation in modelsim
- how can i save my received data into the SDRAM?
- Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
- Update Picoblaze Code in Bitstream
- V4 vs. Stratix-II...
- EDK 7.1 with xilinx ML401 ref design
- To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
- "Mine is bigger than yours..."
- Re: Counting Clocks
- How to turn off auto bufg insertion in ISE 7.1 ???
- initializing fifo pointers to simulate overflow
- High radix multiplier
- Auto-select clock for virtual pins
- Input Maximum Delay timing assignment in Altera
- EDK 7.1 XMD and platform USB cable
- Tutorial on debug of packet processing in FPGA hardware using Identify
- How to use XMD debugger
- Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
- Minimum circuit to get Spartan-3 running
- Slice Virtex II = Equivalent gates ??
- Analog to Digital Converted (ADC) & Spartan 3
- how to use libm.a and libc.a
- Frequency limitations?
- FPGA/Embedded Design Training
- Test the code on FPGA Board...
- strange Microblaze error
- Any Virtex 4 development/prototyping boards out there???
- An FPGA eval board at $49!!
- ACTEL design problems
- Xilinx versus Elixent; other radically different concepts?
- 2.5/3.3 LVPECL in Virtex
- Add on bus
- Virtex4 running at 360Mhz DDR
- dividing the clcok by 2.5
- PCI PCIX LoGi Core Problem
- CAM implementation on Lattice EC
- Clock speed problem. How can I proceed?
- Configuring an XC3S400 Spartan 3 with JTAG
- DDR speed of the XUPV2P Board from Digilent
- Altera Quartus Timing Models
- dcm's for increasing clock speed
- Altera: Maxplus rules!
- TRACE and Modelsim Timing Help
- Uart16550 can't receive data over 16byte a time
- Quartus II - multicyle option
- Xilinx VIIPro mixed configuration voltages
- 8051 IP core
- true dual port memory v/s simple dual port memory
- how to add library
- Max7000ae and GCLRn
- Flagging XST to suppress the warning
- EDK: user logic on opb bus in microblaze system
- Looking for Xilinx Power-PC consultant
- Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
- Fake Buffers in ECS
- float computing: how to add libm.a
- Clock delay vs. clock skew
- how can i add my math library libm.a in my project
- how can i join the comp.arch.fpga group
- IP core supply
- Which chip should I use?
- Metastability / MUX question
- Xilinx ISE 6.3 verilog simulation problem
- 40% less SEU's! in V4: another good reason to choose Xilinx
- newbie question
- Cant link with xil_malloc() function
- Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
- Will this DCM cascade track a frequency offset clock?
- on chip termination for DVI (TMDS) possible?
- Using capacitor to slow the rise time.
- Parallel Cable IV opened in "Compatibility Mode"
- FPGA choice advice needed
- creating testbench with data from logic analyzer
- GSPx 2005 Call for Papers
- Spartan-3 boards comparison
- quantization and rate control
- re:How to control peripheral say a small DC motor using ML300
- EDK "libSecurity.dll"
- How to control peripheral say a small DC motor using ML300
- including components, i.e. SRL16
- DVI implementation
- Clock Gating
- VIIPro on-chip LVDS termination
- MicroBlaze latencies
- System Ace: How many FPGA's in the JTAG chain before require buffers?
- Xilinx Prom programming
- how to constrain this
- Altera SDRam ip core
- How to add DCM as customized IP using FSL channel
- Help
- Does this group allow JobPostings?
- Does this group allow JobPostings?
- Newbie VHDL/FPGA question
- Saturating an integer
- Availability of the Xilinx ML481 Development Board
- embedded linux for v2pro PPC?
- New Altera Software Dev Board with VGA full color?
- Gated clock problem
- ERROR: NgdBuild:604 - logical block
- Altera Excalibur EBI problem
- Simulating custom peripherals
- VHDL help with adding modules
- Multiply Accumulate FPGA/DSP
- Negative hold time from Quartus
- DCM, constraints and routing (Xilinx Spartan 3)
- Max freq. of operation in FPGA?
- Memec/Insight LX25LC Board Flash Troubles
- JTAG without parallel port
- JTAG communication Problems in Quartus using Signal Tap
- Re: Force sequential assigment
- Force sequential assigment
- 200+ MHz through a SCSI cable
- writing with impact to eeprom
- Performing Readback from Impact
- Xilinx V4 Power Calculations
- WTB: Xilinx 6.2i EDK
- Frequency Limit !!
- OPB Intc - HELP !!!!
- Reasonable Entry Level Dev. Board....
- Virtex4 and ISE reality check?
- Microblaze FSL interface timing diagram
- cross clock timing constraints
- Cheap PowerPC G4 PCI coprocessor board for the PC
- PCI-X target chip with simple backend interface....
- Xilinx input path: Why does the optional delay element with inputFFhelp me?
- Xilinxs XCF16 PROMS Eng. Samples Bugs?
- current price for (small quantity) XC4VFX12/FF668
- Decoupling V2P
- FPGA Article on Slashdot.
- VGA sync signals
- problems getting flex10k10 to work
- using cadence tool
- Median Filter for floating points
- Nuhorizons alternatives for Xilinx parts?
- Patent issues in implementing embedded fpgas
- signals in modelsim
- how can I improve my code?
- Lvds input problem urgent
- Problem with JTAG server on Quartus 4.0 for XP
- Map Error: "RLOC not supported for simple gates"
- Gated Clock Timing
- How to implement this C function in FPGA
- FPGA applications in RFID
- crazy behaviour of fpga, timing ?
- Xilinx FPU for Virtex-4 over FPU
- Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
- Flexray ip core
- Formal verification tool?
- clk-pad, ibufg, dcm Problem
- MIcroblaze FSL Datasheet
- Change OCM Clock
- Signal use from pin
- XPS vs. Project navigator
- Cygwin & Nios II
- DCM Cycle-to-Cycle Jitter
- LM4550 Audio Codec
- EDK 7.1 : ML40x / ML401 Reference Design
- LM4550 AC97 Codec on the XUP board
- LM4550 AC97 Codec on the XUP board
- LM4550 Audio Codec
- RocketIO decoupling
- obufds attribute problem
- x on ml300?
- XC9500 - creating RS485 Mux
- XC9500 - creating RS485 Mux
- Virtex slow clock multiply options?
- Synplify warning CL209
- Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1
- Proper use of BUFGMUX and DCM in Spartan 3
- RocketIO attribute for TLK3101 or TLK2501?
- RocketIO attribute for TLK301 or TLK2501?
- RocketIO attribute for TLK301 or TLK2501
- XC4k parts obsolete ?
- ISE wishlist
- MAX II UFM data specification and programming
- Rom Inference
- Memec JTAG cable IJC-3
- dynamic size of ports
- PCI plug n play and Graphics card implementation
- Bus Frequency !!
- quartus_pgm under Linux?
- Sync + FIFO
- webpack for os x or freebsd ?
- questions on Xilinx Virtex-4 to DDR SDRAM module
- Help creating a System Ace file
- Experience with Hitech Global & Xilinx
- bad syncronous description
- what is microblaze ?
- [Sparan-II] Internal Power-On Reset Block?
- ml310: linux boot faillure
- Executing program from external memory
- Space Invaders!
- New FPGA Development Board
- slow peripherals and modelsim
- "Correct design" and practical trouble and simulation trouble butwhy
- simple delays
- Platform Cable USB & ISE 7.1 & Linux
- Relative number of CLBs
- READ/WRITE files using TEXTIO using Quartus
- motherboard w/o 3.3V PCI fingers
- WTB Xilinx Ver. 6.2 EDK
- how to put an FIR in an FPGA?
- is the 8051 architecture public domain?
- playxsvf file501b
- "Implement Design" Error on ISE 6.3 webpack
- multiplier with one fixed value other user defined
- DDR SODIMM on Avnet Virtex II PRO development kit
- Time Borrowing