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  1. Why do VHDL gate level models simulate slower than verilog
  2. where are the PAO files for the system.bsp stored???
  3. XPS: Create/Import File structure
  4. Problems with Constraints (Xilinx, ISE 6.3)
  5. DDR2 based Xilinx Development boards ?
  6. Q, BRAM initializing using INIT_0X
  7. For accessing my SDRAM,what should i do?
  8. Linux on Xilinx ml310
  9. CORDIC bit-serial vs. bit-parallel
  10. Xilinx IP: PCI Express
  11. Detaching the schematic viewer under ISE Webpack
  12. VHDL array question
  13. About back annotated simulations...
  14. Which Simulators
  15. Jam Byte-Code Player for 8051
  16. Virtex 4 MGTVREF pin reference circuit
  17. open support question to Xilinx. should be fairly simple to answer.
  18. Virtex-2 JTAG problem
  19. Help needed!!interrupt handling in microblaze system
  20. delays
  21. edk sram interface - board definitions files xbd
  22. Registers replication on Xilinx IOBs
  23. Is a gated oscillator using NAND okay within a Cyclone FPGA?
  24. Bullshit Achieves Literary Status
  25. Silicon Valley FPGA position
  26. Altera Apex20KE PLL output jitter problem
  27. why is it wrong with "sin"?
  28. Xilinx : Clock Swallowing
  29. SPI interface cpol & cpha
  30. wide ROM
  31. Microblaze interrupt problem
  32. Universal logic modules vs NAND-like modules
  33. Serial communication
  34. FPGA design under Mac OS X ?
  35. Quartus II Fitter Problem
  36. Virtex-II Switch Matrix Performance
  37. floorplanning
  38. microblaze and 64 bit memory over PLB bus
  39. Whats going on here?
  40. Handling Interrupt
  41. Tristate-Master-Slave testbench description
  42. PowerPC and application in external RAM
  43. Q)BRAM VHDL simulation in modelsim
  44. how can i save my received data into the SDRAM?
  45. Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
  46. Update Picoblaze Code in Bitstream
  47. V4 vs. Stratix-II...
  48. EDK 7.1 with xilinx ML401 ref design
  49. To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
  50. "Mine is bigger than yours..."
  51. Re: Counting Clocks
  52. How to turn off auto bufg insertion in ISE 7.1 ???
  53. initializing fifo pointers to simulate overflow
  54. High radix multiplier
  55. Auto-select clock for virtual pins
  56. Input Maximum Delay timing assignment in Altera
  57. EDK 7.1 XMD and platform USB cable
  58. Tutorial on debug of packet processing in FPGA hardware using Identify
  59. How to use XMD debugger
  60. Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
  61. Minimum circuit to get Spartan-3 running
  62. Slice Virtex II = Equivalent gates ??
  63. Analog to Digital Converted (ADC) & Spartan 3
  64. how to use libm.a and libc.a
  65. Frequency limitations?
  66. FPGA/Embedded Design Training
  67. Test the code on FPGA Board...
  68. strange Microblaze error
  69. Any Virtex 4 development/prototyping boards out there???
  70. An FPGA eval board at $49!!
  71. ACTEL design problems
  72. Xilinx versus Elixent; other radically different concepts?
  73. 2.5/3.3 LVPECL in Virtex
  74. Add on bus
  75. Virtex4 running at 360Mhz DDR
  76. dividing the clcok by 2.5
  77. PCI PCIX LoGi Core Problem
  78. CAM implementation on Lattice EC
  79. Clock speed problem. How can I proceed?
  80. Configuring an XC3S400 Spartan 3 with JTAG
  81. DDR speed of the XUPV2P Board from Digilent
  82. Altera Quartus Timing Models
  83. dcm's for increasing clock speed
  84. Altera: Maxplus rules!
  85. TRACE and Modelsim Timing Help
  86. Uart16550 can't receive data over 16byte a time
  87. Quartus II - multicyle option
  88. Xilinx VIIPro mixed configuration voltages
  89. 8051 IP core
  90. true dual port memory v/s simple dual port memory
  91. how to add library
  92. Max7000ae and GCLRn
  93. Flagging XST to suppress the warning
  94. EDK: user logic on opb bus in microblaze system
  95. Looking for Xilinx Power-PC consultant
  96. Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
  97. Fake Buffers in ECS
  98. float computing: how to add libm.a
  99. Clock delay vs. clock skew
  100. how can i add my math library libm.a in my project
  101. how can i join the comp.arch.fpga group
  102. IP core supply
  103. Which chip should I use?
  104. Metastability / MUX question
  105. Xilinx ISE 6.3 verilog simulation problem
  106. 40% less SEU's! in V4: another good reason to choose Xilinx
  107. newbie question
  108. Cant link with xil_malloc() function
  109. Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
  110. Will this DCM cascade track a frequency offset clock?
  111. on chip termination for DVI (TMDS) possible?
  112. Using capacitor to slow the rise time.
  113. Parallel Cable IV opened in "Compatibility Mode"
  114. FPGA choice advice needed
  115. creating testbench with data from logic analyzer
  116. GSPx 2005 Call for Papers
  117. Spartan-3 boards comparison
  118. quantization and rate control
  119. re:How to control peripheral say a small DC motor using ML300
  120. EDK "libSecurity.dll"
  121. How to control peripheral say a small DC motor using ML300
  122. including components, i.e. SRL16
  123. DVI implementation
  124. Clock Gating
  125. VIIPro on-chip LVDS termination
  126. MicroBlaze latencies
  127. System Ace: How many FPGA's in the JTAG chain before require buffers?
  128. Xilinx Prom programming
  129. how to constrain this
  130. Altera SDRam ip core
  131. How to add DCM as customized IP using FSL channel
  132. Help
  133. Does this group allow JobPostings?
  134. Does this group allow JobPostings?
  135. Newbie VHDL/FPGA question
  136. Saturating an integer
  137. Availability of the Xilinx ML481 Development Board
  138. embedded linux for v2pro PPC?
  139. New Altera Software Dev Board with VGA full color?
  140. Gated clock problem
  141. ERROR: NgdBuild:604 - logical block
  142. Altera Excalibur EBI problem
  143. Simulating custom peripherals
  144. VHDL help with adding modules
  145. Multiply Accumulate FPGA/DSP
  146. Negative hold time from Quartus
  147. DCM, constraints and routing (Xilinx Spartan 3)
  148. Max freq. of operation in FPGA?
  149. Memec/Insight LX25LC Board Flash Troubles
  150. JTAG without parallel port
  151. JTAG communication Problems in Quartus using Signal Tap
  152. Re: Force sequential assigment
  153. Force sequential assigment
  154. 200+ MHz through a SCSI cable
  155. writing with impact to eeprom
  156. Performing Readback from Impact
  157. Xilinx V4 Power Calculations
  158. WTB: Xilinx 6.2i EDK
  159. Frequency Limit !!
  160. OPB Intc - HELP !!!!
  161. Reasonable Entry Level Dev. Board....
  162. Virtex4 and ISE reality check?
  163. Microblaze FSL interface timing diagram
  164. cross clock timing constraints
  165. Cheap PowerPC G4 PCI coprocessor board for the PC
  166. PCI-X target chip with simple backend interface....
  167. Xilinx input path: Why does the optional delay element with inputFFhelp me?
  168. Xilinxs XCF16 PROMS Eng. Samples Bugs?
  169. current price for (small quantity) XC4VFX12/FF668
  170. Decoupling V2P
  171. FPGA Article on Slashdot.
  172. VGA sync signals
  173. problems getting flex10k10 to work
  174. using cadence tool
  175. Median Filter for floating points
  176. Nuhorizons alternatives for Xilinx parts?
  177. Patent issues in implementing embedded fpgas
  178. signals in modelsim
  179. how can I improve my code?
  180. Lvds input problem urgent
  181. Problem with JTAG server on Quartus 4.0 for XP
  182. Map Error: "RLOC not supported for simple gates"
  183. Gated Clock Timing
  184. How to implement this C function in FPGA
  185. FPGA applications in RFID
  186. crazy behaviour of fpga, timing ?
  187. Xilinx FPU for Virtex-4 over FPU
  188. Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
  189. Flexray ip core
  190. Formal verification tool?
  191. clk-pad, ibufg, dcm Problem
  192. MIcroblaze FSL Datasheet
  193. Change OCM Clock
  194. Signal use from pin
  195. XPS vs. Project navigator
  196. Cygwin & Nios II
  197. DCM Cycle-to-Cycle Jitter
  198. LM4550 Audio Codec
  199. EDK 7.1 : ML40x / ML401 Reference Design
  200. LM4550 AC97 Codec on the XUP board
  201. LM4550 AC97 Codec on the XUP board
  202. LM4550 Audio Codec
  203. RocketIO decoupling
  204. obufds attribute problem
  205. x on ml300?
  206. XC9500 - creating RS485 Mux
  207. XC9500 - creating RS485 Mux
  208. Virtex slow clock multiply options?
  209. Synplify warning CL209
  210. Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1
  211. Proper use of BUFGMUX and DCM in Spartan 3
  212. RocketIO attribute for TLK3101 or TLK2501?
  213. RocketIO attribute for TLK301 or TLK2501?
  214. RocketIO attribute for TLK301 or TLK2501
  215. XC4k parts obsolete ?
  216. ISE wishlist
  217. MAX II UFM data specification and programming
  218. Rom Inference
  219. Memec JTAG cable IJC-3
  220. dynamic size of ports
  221. PCI plug n play and Graphics card implementation
  222. Bus Frequency !!
  223. quartus_pgm under Linux?
  224. Sync + FIFO
  225. webpack for os x or freebsd ?
  226. questions on Xilinx Virtex-4 to DDR SDRAM module
  227. Help creating a System Ace file
  228. Experience with Hitech Global & Xilinx
  229. bad syncronous description
  230. what is microblaze ?
  231. [Sparan-II] Internal Power-On Reset Block?
  232. ml310: linux boot faillure
  233. Executing program from external memory
  234. Space Invaders!
  235. New FPGA Development Board
  236. slow peripherals and modelsim
  237. "Correct design" and practical trouble and simulation trouble butwhy
  238. simple delays
  239. Platform Cable USB & ISE 7.1 & Linux
  240. Relative number of CLBs
  241. READ/WRITE files using TEXTIO using Quartus
  242. motherboard w/o 3.3V PCI fingers
  243. WTB Xilinx Ver. 6.2 EDK
  244. how to put an FIR in an FPGA?
  245. is the 8051 architecture public domain?
  246. playxsvf file501b
  247. "Implement Design" Error on ISE 6.3 webpack
  248. multiplier with one fixed value other user defined
  249. DDR SODIMM on Avnet Virtex II PRO development kit
  250. Time Borrowing