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  1. Xilinx LVDS and SCSI
  2. trouble trying to debug c code on MicroBlaze
  3. Suche FPGA Protoboard
  4. Pb with an IPCore Dual Port Memory
  5. Searching FPGA board for private use
  6. xilinx ml310 : to run applications on 2 nd ppc
  7. Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
  8. How to pipeline Loop Logic?
  9. OrCAD Symbol For Xilinx V2PRO
  10. Best Practices for Hardware Designers
  11. Synplify vs XST...
  12. FPGA or SSE2 ?
  13. Selecting FPGA synthesis, place and route and simulation tools
  14. FPGAFLASH
  15. linker script!!!
  16. computer upgrade time.
  17. ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
  18. XPS : Body of function not found
  19. Body of function not found
  20. xmodem/kermit for edk/ppc
  21. set seed in 6.2i or 6.3i -timing?
  22. A lot of trouble when trying to debug c code on MicroBlaze
  23. Building a MicroBlaze from scratch, unable to run.
  24. X-Fest devkit order leadtimes & software silliness....
  25. Gated clock question
  26. S3 not auto-loading from platform flash
  27. programmation with IMPACT with one PROM and two FPGAs
  28. fast universal compression scheme and its implementation in VHDL
  29. SPD interface(Serial presence detect)
  30. I2C clock stretching(XILINX reference design)
  31. Question for Alex Gibson
  32. JTAG programming: JAM files versus ISC (IEEE1532) files
  33. Persist option in bitgen
  34. ISE tools to use SMP?
  35. Synplify/Quartus used to support direct to Hardcopy?
  36. pcb layers on BGAs Spartan-3
  37. execute ppc code from external ram
  38. Mapping Dual Port Ram into Microblaze address space
  39. How to convert Matlab to HDL?
  40. Ml40x Reference Design not working with EDK 7.1?
  41. Lattice LFEC20 DDR SDRAM connection
  42. Motion controller design with CPLD
  43. Motion controller design with CPLD
  44. Motion controller design with CPLD
  45. Motion controller design with CPLD
  46. DDR desing with FPGA
  47. anyone tried the Actel ProASIC3 Starter Kit?
  48. [Vir2] Can I use a 18k ram as 2 single-port ram?
  49. In-system configuration
  50. linker script
  51. Memory management : microblaze system
  52. Available under the terms of the SignOnce IP License
  53. searching spartan-3
  54. QuickLogic FPGA : In-Circuit Programming
  55. Boot problem Stratix Kit EP1S25
  56. Connecting two INOUT ports
  57. false path on asyn. fifo
  58. why my SDRAM test failed in EDK7.1i?
  59. Atmel CPLD development tools for verilog
  60. How to deal with misplaced module in ISE?
  61. [Verilog] How to write a barrel shifter?
  62. Anonymous structs in Microblaze C compiler
  63. faster Spartan III adder
  64. Nios Stratix
  65. ISE/EDK 6.3 vs 7.1...
  66. Lattice and Mentor seminar info pieces...
  67. Measuring DDR SDRAM
  68. Placing variables at a specific location (address) using microblaze GCC
  69. VirtexII:DCM:CLKFX phase delay
  70. nios32 -> nios2 assembly porting?
  71. Simulation problems virtex II
  72. Virtex2 simulation madness
  73. Fast/low area Sorting hardware.
  74. Signed/unsigned divider
  75. PowerPC crash down
  76. FPGA I/O pin current sink
  77. How do I find out the connection of the LCD I took out from a digital camera?
  78. Upgrading the EDK from 6.3
  79. Little Problem with EDK 7.1 (Errors while compiling)
  80. board-level simulation?
  81. Xilinx ISE 7.1i
  82. Sch & Layout Free Program
  83. Clock doubler to double an input 13.5 Mhz
  84. FPGA/CPLD trend
  85. Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
  86. Hope for OS X tools...
  87. Pissed off with Xilinx - Spartan 3
  88. Spartan 3 Starter kit group formed
  89. IC engineer or Embedded system software engineer?
  90. problem with bitstream file in ChipScope Pro analyzer ..
  91. Generating linker script for Altera desgn
  92. Microblaze 4.0 with uClinux is ok or not?
  93. 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
  94. how to use FPU with EDK7.1i
  95. Anyone has datasheet for the LCD on a Palm's Tungsten W?
  96. Xilinx + ModelSim XE Linux
  97. ORCAD CIS 7.2
  98. TI TMS320 DSP as a soft-processor in FPGA?
  99. *.mcs format file can't contain over 1Mbyte data?
  100. How to get *.mcs file containing both *.bit and *.elf file, to port linux on my memec virtex-ii board.
  101. FPGA : MAC FIR doubt--HELP ME PLEASE
  102. Xilinx ISE Webpack download problem
  103. Query - ChipScope Pro analyzer
  104. Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
  105. Share one BRAM block between user logic and microblaze (Spartan3)
  106. edk 6.3 : INTERNEL_ERROR
  107. not clear about doing power estimation using xpower
  108. MediaBench
  109. ispLSI1016
  110. isplsi1016
  111. Boot problem Stratix Kit EP1S25
  112. XP for NIOS2
  113. ISE under Linux: 32 vs 64 bits
  114. Protecting IP in China
  115. keypad scanner
  116. how can i extend my code space to extern memory?
  117. Spartan 3 ata interface
  118. How do I instantiate GT11CLK_MGT?
  119. UARTlite problem..!!!
  120. Basics FPGA
  121. ppc405 cache using bram
  122. some mistakes with EDK7.1i
  123. Altera's fast NIOS update service (o;
  124. How to add a lib to the core used
  125. PCI master clock trace
  126. FPGA : Coregenerator Adaptive FIR Filter
  127. USB interface With AMBA AHB
  128. Clock Generation : FPGA
  129. How to speed up float computing--continued
  130. how to use GCC compiler
  131. file differece for two xsvf files
  132. using 8051 and converted XSVF to download Spartan3
  133. Quick way to synthesize pcores in EDK
  134. C-1 how to reflash..
  135. Test
  136. mc8051 v1.4 free ip core from Oregano Systems
  137. Xilinx -- iMPACT -- Parallel Port [JTAG Cable] Cable connect
  138. Chipscope and LVDS clock (IBUFGDS)
  139. why can't i use opb_spi core in EDK6.3?
  140. Query -V2Pro fpga programming
  141. Anybody know cost/supplier for Virtex-4 LX40?
  142. Spartan 3 kit FPGA configuration problem
  143. How to speed up float computing
  144. problems with Ultra DMA operations with ATA HDD
  145. problem with edk 7.1
  146. need a book: Hilbert transform
  147. Implementing sin function in fpga
  148. regional clk to dcm? possible or not?
  149. How fast multiplier in VirtexE?
  150. Altera NIOS2 50.0 SOPC periphals broken???
  151. Xilinx DDR output registers
  152. JTAG Programming Problem
  153. Problem with Synplify 7.7.1, startup block vs clock input
  154. What is a typical job scope when FPGAs are involved?
  155. Configuration-Frames for Virtex-II (Pro)
  156. Accessing Bram
  157. opb bram controller
  158. Timing summary
  159. Problems with SDRAM and Altera Cyclone
  160. program simulation of the ML310 with XPS+ModelSim
  161. Nios II - Booting software from Flash
  162. Magical Mystery Tour of ISE environment variables
  163. StateCAD 7.1i is broken?
  164. Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1
  165. Nios speed down
  166. SPI slave select signals
  167. Xilinx ISE 6.1i - Fatal Error
  168. ISE 6.1 - Fatal Error
  169. Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
  170. Keypad controller implementation
  171. [NEWBIE] Linux WebPack questions...
  172. beginer
  173. Control asynchronous SRAM like synchronous SRAM
  174. FPGA Boards
  175. Synplify 8.1 vs. Quartus II 5.0 QoR
  176. Incremental Compilation in Quartus 4.2
  177. Incremental Comilation in Quartus 4.2
  178. Hard Ethernet MAC for Virtex-4 FX12
  179. Design flow of Spartan3 for my own embedded processor and HW logic?
  180. Accessing BRAM as a SRAM
  181. Wrong type name (subtitution) in post-place & route simulation model.
  182. Xilinx Parallel Cable III flying lead repair
  183. compact flash configuration on ml403 board
  184. Q.Timing Simulation using ModelSim for a Xilinx Spartan 2E
  185. ISE 7.1 small advice about project files (.ISE extension)
  186. 2:1 mux in one LUT
  187. Async FIFO coregen wizard
  188. Postal Lottery: Turn $6 into $60,000 in 90 days, GUARANTEED
  189. V2pro configuration problem - PROM SIZE
  190. What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
  191. State Machines.. and their efficiency.
  192. ARC A4
  193. Virtex 4 configuration frames
  194. Ethernet / digital logic questions
  195. lpm_counter bug?
  196. generate systemACE file
  197. powerpc startup
  198. Single-endec clocks
  199. Lattice ROM file tool....
  200. warning place and route ise7.1?
  201. Bresenham Algorithms
  202. FS: Surplus Electronics From Old Projects - Altera Xilinx Linear Tech Maxim & HP & More
  203. Programmer + Cable
  204. cannot get compedklib tool to work
  205. ethernet
  206. Xilinx Answer Record 21127
  207. using a SDRAM FIFO
  208. how to apply different stimulus files to a test bench
  209. Xilinx Virtex 4 Configuration Frames
  210. QUARTUS on Linux.
  211. Mapping problem due to invalid pins in UCF file
  212. 2006251 CD-R, DVD R, DVD CASES LOWEST PRICE! 20
  213. System Reset / GSR with Virtex 2 & Virtex 4
  214. Project Navigator mapping problem with CLK and BRAM
  215. more and more and more issues with Xilinx tools
  216. Nondeterministic ISE Placement
  217. CPLD Fitting problem
  218. RISCWatch and JTAG
  219. using less brams for powerpc code
  220. FSM stops working
  221. Virtex4 Block Ram : ISE6.3 Problem
  222. spartan 3 designing board
  223. GHDL under x86_64 Linux
  224. Looking for core that does a vector product
  225. Custom IP and BFM simulation help
  226. student round table
  227. How to make a 1.44MHz clock?
  228. Reading the contents of a FPGA in-circuit.
  229. VHDL vs. Schematic Capture
  230. Here it is. The smoking gun.
  231. How to download uClinux on Virtex4 Board.
  232. ALTERA EPXA1 SDRAM BUG
  233. Memec Virtex-4 LX25 LC
  234. Synopsys Designware IP... can be used for Xilinx FPGA??
  235. A Short Pulse Catcher
  236. FFT with FPGA
  237. Jobs going in New Zealand
  238. Simulation of rocket IO in virtex 2 pro
  239. ISE and Linux
  240. Serial Input Review and Questions
  241. Coloring by clock?
  242. Xilinx Webpack on Gentoo-64bit ?
  243. Pushing PicoBlaze
  244. Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
  245. Spartan 3 CPI
  246. Xilinx V2Pro DCM config and settling time questions
  247. how to debug a C/C++ application in NIOS II IDE
  248. Actel Designer on Linux
  249. Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
  250. How many logic cells are there in one slice