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  1. Stacked Die devices
  2. Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
  3. Resampling in FPGA with irrational or large rational ratios
  4. Max Sample Rate for Signal Tap in Altera Quartus?
  5. Verilog Coding Guidelines
  6. Verilog Coding Guidelines
  7. QAM 64 implementation on a FPGA board
  8. Bit serial, book, other info???
  9. aurora reliability
  10. Recommend www.edaboard.com
  11. SELV - power supply specification
  12. Problems with Timing Simulation
  13. about fast adder
  14. Actel vs. Xilinx and Altera
  15. Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
  16. for sale: two spartan-3 dev boards, $50 each (normally $100)
  17. PC104 (ISA) bus in FPGA (Spatan 2E)
  18. Cheking out Linux Kernel Source
  19. Spartan3 pci above 33MHz
  20. Spartan II 2s200 PCI Board
  21. Triggering and reseting FF
  22. virtex4 evaluation board
  23. Program from external memory
  24. PowerPC interrupt
  25. EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
  26. fastest FPGA speed grade?
  27. VHDL Clock Domains
  28. Stratix open-drain pins
  29. Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem)
  30. VPR fundaes
  31. PS/2 interface
  32. Connecting ADC to Opb_Spi core
  33. Virtex-2 Pro: Configuration Frames
  34. Ethernet FPGA development board
  35. nios2 toolchain sources...
  36. EDK 6.3, Xilinx ML40x ML402, XBD files
  37. Call for FPGAworld 2005
  38. Xilinx IOB flop mapping vs. -bp switch
  39. DDR controller : problems about burst access
  40. xapp 482 and add custom function
  41. ModelSim Timing Simulation Signal Names
  42. Xilinx: XST synchronous FIFO using BRAMs
  43. test
  44. FPGA system RAM
  45. Foundation 3.1 in WinXP machine Problems!
  46. vhdl source code cross reference tool
  47. interpolation in FPGA
  48. Avnet V4 - XC4VLX25
  49. Cyclone Board with // LVDS lines
  50. RENTABLE
  51. Direct audio output from FPGA pins
  52. LogiCore: SGMII autonegotiation
  53. Avnet V2P development kit woes
  54. FPGA development board - urgently
  55. aurora framing
  56. Coverting .mcs file to .bit file
  57. ip core supply
  58. PROM Generation question
  59. init ProASIC3 Ram from spi
  60. from email into FPGA !!
  61. TDI routing in Virtex E FPGA.
  62. Cannot find net in ucf, but it's there....
  63. XST: setting top-level generics
  64. PPC405 Question
  65. PPC405 Question
  66. Cyclone online store
  67. edn macro in ISE
  68. Clock buffering in VirtexE FPGA
  69. synthesis problem
  70. Hex files in simulation
  71. Quatech SPP-100 programs/verifies successfully but device is not "programmed"
  72. read & write on SDRAM speed with PPC 300 MHz
  73. ADPLL for NRZ
  74. Small FPGA
  75. xp3/xp6 in ispLever
  76. Linux 2.6 on the Xilinx ML310 board
  77. Clock buffers on the Viretx E
  78. Soft core for MPEG codec
  79. Xilinx Virtex 4 device technology
  80. APEX 20K PLL
  81. INFO:Par:252 - The Map -timing placement will be discarded
  82. WTB FutureElectronics Cyclone NiosII Kit
  83. V4 and NBTI question, again..
  84. CPU address to OCM address translation
  85. proth siever in FPGA?
  86. Control IPIF signals
  87. Good FPGA for an encryptor
  88. USB 2.0 core with 1.1 tranceiver problem
  89. experiences with Summit Visual Elite
  90. Maintaining a Pipeline
  91. Cant' make SignalTap works...
  92. FPGA for video processing
  93. FPGA PC104 development board
  94. multiprocessing with microblaze ?
  95. Spartan ii Slave Serial programming
  96. Poor PCI performance during read accesses (in master mode)
  97. vsync on dvi
  98. Individual study-activity on FPGA's - which subsubject?
  99. Rising to falling edge constraints on Actel ProAsic
  100. Two Verilog FSM style compare
  101. Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
  102. unisim for synthesis?
  103. good bye nios (o;
  104. Chess & FPGAs
  105. dedicated NEWS server for FPGA world
  106. interfacing to multiple converters
  107. Updating FPGA SPROM firmware over the IP network?
  108. Module integration, odd state machine behaviour (verilog), etc!
  109. Memory Controller and State Machine
  110. State of unused pins in Spartan II.
  111. doubt regarding code generator
  112. V4 and DDR2 666
  113. FPGA vs. ASIC vs. Processor
  114. LVTTL Spec
  115. PLB registers
  116. How do I convert a polynomial into a parallel scrambler formula?
  117. How do I convert a polynomial into a parallel scrambler formula?
  118. Spartan-3e order of availability?
  119. Need help for Xilinx FPGA
  120. Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
  121. XILINX DCMs and synthesis results
  122. Cyclone Dev. Board, how to set lower clk freq?
  123. iMPACT downloading error
  124. nios2 gnu sources broken for amd64 linux
  125. NIOS2 subscription online?
  126. ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL
  127. How about signed adder?
  128. Xilinx Impact-Tool: Error when downloading partial bitstream
  129. using GUI and batch mode produces different results !
  130. Chipscope problem
  131. FPGA :FFT Core in Xilinx
  132. Minimum allowed clock frequency for Nios 2 processor (Stratix 2)
  133. Virtex-4 FX devices availablity issues
  134. DC Offset removal in FPGA
  135. Xilinx Powe Requirements V2PRO complaint
  136. problems with Xilinx GSRD design for ML403
  137. Commercial Z180 / 64180 core
  138. User Core to PLB Bus example for Virtex 2P in EDK.
  139. Serial I/O - Delay Output
  140. FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)
  141. Need some help with understanding MDM
  142. simple SRAM memory controller Avnet V2P development board
  143. Virtex 4 and reconfigurable computer
  144. DES core for Xilinx Virtex 2Pro for the EDK and PLB
  145. reading file from CF with 4VSX35 and EDK
  146. Need help understanding this AHDL code
  147. Frequency divisors
  148. ISE 7.1 - block memory init value issue during simulation
  149. Need help with AHDL
  150. disappointed with Altera this time
  151. ppc 405 in debug halt mode
  152. Setting ucf for DLLs:Urgent
  153. FPGAs and JTAG
  154. Difficult in probing through chipscope
  155. FPGAs in Cray XD1
  156. Area_Group
  157. choosing an fpga board
  158. DC vhdl question
  159. Low cost altera board
  160. Altera Net Seminar on 3GPP Release 6 and Beyond
  161. dru files for eagle ?
  162. [XILINX][V2PRO]IOB tristate pins.
  163. JTAG port access in Cyclone
  164. TDM over Aurora
  165. nios2 / terminal
  166. Altera SCFIFO
  167. FPGA Filter Design
  168. Post Translate Timing
  169. Real Example of Xilinx IPCore Instantiation
  170. System Generator
  171. 5 Volt tolerance - Altera
  172. Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
  173. [SPARTAN-3]: Parts Back on Xilinx Online Store (www.xilinx.com/store)
  174. Speeding up FPGA designs
  175. BIG PROBLEM : Configuration Boot Problem Stratix
  176. Xilinx MacFir5.0 - Block Ram requirenments
  177. How to reset a PLB/OPB Peripheral
  178. ISE 7.1 Service Pack 2 - Ready yet?
  179. Need Application note for Motion Controller with Xilinx
  180. use lattice and actel synplify together...
  181. Retrieving code from an old PAL
  182. FPGAs: Where will they go?
  183. Xilinx LPT programmer help
  184. Xilinx webshop
  185. Microblaze address space and variables
  186. Spartan 3 availability
  187. globally asyncronous vs locally syncronous?
  188. Lattice LFEC
  189. Re: Idea exploration - Image stabilization by means of software.
  190. clock domain : DDR read enable
  191. damage Atmel AT40k/AT94k with wrong bitstream?
  192. Ideal CPU for FPGA?
  193. CPLD fusemap data - why the secrecy?
  194. SystemC comments
  195. Interesting question on CPLD
  196. circuit optimization - a feedbackless machine
  197. Xil_FatFS library example.
  198. Update on availability of Spartan3
  199. area group constraint for quadranting
  200. Lean Ethernet on Digilent board?
  201. Xilinx FFT
  202. Xlinix configuration: DONE pin too early?
  203. Error :device requires cache coherent memory for BD's
  204. Free Xilinx Cable III for owners of Altera MAX2 Starterkit.
  205. comp.arch.fpga.<mfr>
  206. IPIF LogiCore?
  207. Atmel tools: any way to edit intra-cell connections in IDS/Figaro?
  208. PCI in a PCI-X slot
  209. AbusivepPricing information in marketing publications
  210. question about xilinx micro kernel
  211. Need application note for Motion controller with Xilinx
  212. USB2.0 UTMI Free IP Core Implentation
  213. Xilinx Spartan 3 DCI Power Consumption
  214. Xilinx
  215. Xilinx
  216. what's my problem with downloading?
  217. Idea exploration 1.1 - Inertia based angular sensor.
  218. Good FPGA introduction book ?
  219. BGA Rework/Prototype Placement Anyone?
  220. uart / Nios2
  221. cmo***od
  222. Xilinx MAP problem (>1 External Macro Output Pin on single net)
  223. question regarding "Add I/O buffers" option - SOS
  224. Idea exploration - Image stabilization by means of software.
  225. LUT, how to?
  226. Deisgn partitioning issues
  227. MINI PCI card for testing FPGA MINIPCI core
  228. convert vhdl to edif
  229. Availability of Spartan3
  230. Using BUFGMUX component in Spartan-3
  231. NIOS2 exceptions...
  232. Xilinx seminar is free AND low cost!
  233. Stratix Kit EP1S25 Boot problem
  234. VHDL Synthesis tutorial
  235. VHDL Synthesis tutorial
  236. VHDL Synthesis tutorial
  237. EDK 7.1 installation error: Missing libPortability.dll file
  238. Memec S3-1500 board + P160 comms 2
  239. Where to buy a Xilinx XCR3384XL tq144 CPLD?
  240. errors during MAP
  241. Problem for xilinx!!!
  242. Auto pipeline logic??
  243. question - NGC & NGO files & integration
  244. PCI arbiter doubt
  245. Somewhat OT - falling behind the times ...
  246. generating 90, 180 and 270 shifts
  247. Viewing internal signal in Modelsim (post P&R)
  248. Adding Verilog processing core to Viretx2Pro at ML310
  249. never seen XST error
  250. RAM State Machine Examples