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  1. Spartan-3E Starter Kit availability slips to December
  2. Linux on Viretex-II pro
  3. spartan 3 starter kit auto configuration at power up
  4. Final Call for Participants & fringe CPA 2005 (18-21 Sept 2005) in Eindhoven
  5. WARNING:HDLParsers:3481 - No primary, secondary unit in the file
  6. Cyclone conf flash - 25p10 !
  7. Any GOSPL Docs?
  8. ANN: Altera Power Net Seminar #2
  9. SI newsgroup
  10. Final Call for Participants CPA 2005 (18-21 Sept 2005) in Eindhoven
  11. Partial vector range in instance warning
  12. Spartan 3E and Spartan 3 with GTL
  13. PCI on ML310 Xilinx board
  14. SPARATAN 2E - input clock
  15. Disconnect the FPGA I/O pads from the outside world
  16. Carry saver adder
  17. Quartus2 WEB: Simulating from test bench. Is that possible?
  18. Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."
  19. Area Estimation Issues
  20. PPC405 32 bit aligned accesses
  21. False values in Quartus In-System Memory Editor
  22. Nand Flash Emulator
  23. Fastest input IOB on a Spartan-3?
  24. Defining Environment variables inside EDK
  25. Reprogramming one MAXII EPM1270 vs security bit set
  26. Reading internal signals through a testbench.
  27. coe file of Xilinx MAC FIR core??
  28. Problem with interfacingT-VPACK with ALTERA QUIP5.0
  29. Quartus web edition simulation with off-chip logic?
  30. Partial Reconfiguration : New Forum
  31. Logic??
  32. IC design contract
  33. Long Multiplication
  34. High baud rate chips for RS232 protocol
  35. Modelling latches in Verilog
  36. The best way to sum 8 datas?
  37. Platform Cable USB
  38. Spartan 3 Ram Instantiation
  39. gal16v8 CUPL problems
  40. SI considerations for single chip memory configurations
  41. Creating higher bit multipliers from low bit.
  42. XUP Virtex-II Pro "invalid target architecture"
  43. Modelsim simulation question
  44. Multidimensional port.
  45. Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
  46. OT: CPLD - SimuCAD S/W CD
  47. I2C "SCL" line problem
  48. Xilinx and Lattice tools on one machine?
  49. Modelsim XE and multi-file Verilog projects
  50. FIFO PhysDesignRules:993
  51. Xilinx Virtex II fpga - providing single ended signal to lvds defined pin
  52. current!
  53. MicroBlaze: PLX PCI 9056 IP
  54. Spartan3 PCI SSO(Simultaneously Switching Output) problem
  55. Strange behaviour while trying to program MAX II CPLD's
  56. Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
  57. "Perform Timing-Driven Packing and Placement" error?
  58. New FPGA development board.
  59. A strange behavior
  60. bare die (non packaged) FPGA, CPLD, controllers ?
  61. CPLD CoolRunner-II - IO current limited to 8mA?
  62. Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map)
  63. Mentor FPGA Advantage, a simple question
  64. FS: Lot of 60 XCV1000 FPGAs
  65. FREE stuff through Trialclix
  66. New PCI Express Group
  67. Spartan 3 Serdes
  68. Spartan-3 LVDS driving TFT LCD panel..?
  69. Hello A newbie to FPGA
  70. ZIF press-fit socket for QFP FPGA packages
  71. Problems on Xilinx FIR Core
  72. chipscope commands?
  73. Hi-Z input
  74. modular design: can one use long lines
  75. Low Power RTL Design
  76. Low Power RTL Design
  77. Virtex4 : Downloading error
  78. Version 5.0 of Quartus University Interface Program (for researchers & graduate students) Released
  79. Implementing PLL in Cyclone - Schematic entry
  80. usb and xc95
  81. Re: EDK core wrapping and include files
  82. LCD Interface
  83. Gated clock for FPGA (verilog)???
  84. Quick Xilinx KCPSM3 with verilog question.
  85. UDP problems with Xilinx EDK 7.1
  86. Fine grain vs. Coarse Grain Architectures
  87. Embedded Processors/Serdes
  88. Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
  89. openrisc, jp1 jtag debug utility
  90. 8087 co-processor
  91. beginner [ query : resources and guidance for a newbie]
  92. re:beginner [ query : resources and guidance for a newbie]
  93. Array of slope A/Ds in FPGA?
  94. JTAG conifguration via USB
  95. Checking the PCI master implemented in FPGA
  96. Monitor the internal signal of EDF using chipscope
  97. fast universal compression scheme and its implementation in VHDL
  98. fast universal compression scheme and its implementation in VHDL
  99. Xilinx PC4 Download Cable
  100. Xilinx PC4 Download Cable
  101. Altera nios-debug via JTAG
  102. digilent spartan 3 kit example project
  103. Bootloading with flash-config devices
  104. Maybe a very cool FPGA a throw away idea for Xilinx
  105. Question about program and memory location
  106. CPLD Jitter
  107. mails from Aman Mediratta
  108. How to reduce software size?
  109. Altera Avalon Master/Slave User Defined Logic?
  110. Feedback signal cancellation algorithm
  111. connecting block ram to datapath using bidirectional lines
  112. Clock skew in FPGA Xilinx?
  113. Should I use DCM for every FPGA design?
  114. Mark to initialize BRAM
  115. Problem with ModelSim XE
  116. 36x36 signed multiplier?
  117. infering a BRAM block for a dual ported ROM
  118. SERDES
  119. ISE 7.1 and DCM clkfx
  120. Altera NIOS in a Cyclone
  121. Phase Offset in Xilinx DDS Core
  122. Writing to Spartan 3 SRAM
  123. Bootloader Linker Script Help
  124. SystemACE CF and partial reconfiguration
  125. Issues with Synplify Pro 7.7 synthesis
  126. DMA issues with IPIF on V2P
  127. On a different note: Unable to write edif files in Synopsys Design Compiler
  128. i need some help ASAP !!! (DLL - Spartan-IIE)
  129. Altera ByteBlaster II vs ByteBlaster MV
  130. Microblaze Simple Bootloader
  131. Library of eBooks on FPGA's and other programming stuff
  132. TTL, CMOS and spartan
  133. ADC Clock on Stratix II DSP Dev Board
  134. Single PPC with DES on V2P
  135. Single PPC on Virtex 2 Pro DMA problems
  136. Single PPC on Virtex 2 Pro DMA problems
  137. Single PPC on Virtex 2 Pro DMA problems
  138. Help coding a bigger project
  139. Drive startup mode - PIO write problems from FPGA
  140. fpga_editor and fvwm
  141. Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?
  142. Spartan and Flash PROM : Boundary Scan
  143. what is the difference between "configuring" and "programming"?
  144. Send IP packets at the Ethernet level with VIRTEX4
  145. Strange FPGA problem
  146. Software simulation of hardware evolution
  147. xilinx or digilent
  148. 802.11 IP
  149. Xilinx Xapp482: syncword?
  150. 10 Gigabit Ethernet FPGA boards...
  151. chipscope problems
  152. FPGA Development Board Wish List
  153. Using bootloader
  154. 60 GB IPOD deal found
  155. Xilinx place and route cost table
  156. Xilinx place and route cost table
  157. Stdin / stdout through RS232
  158. DCM does not do anything?
  159. Unused pins from FPGA to LAN91C111 (through NIOS)
  160. Good SystemC tutorials or books?
  161. digilent boards
  162. digilent boards
  163. Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
  164. uDMA Hard drive interface - putting together multiple programs.
  165. Generic Memory-Mapped VHDL Module
  166. Problem in using Hard Macros in Xilinx ISE 7.1
  167. How can I see the waveform of my verilog codes?
  168. chipscope pro 6.3i clocking issue
  169. Problem in timing simulation(Altera)
  170. ISE7.1i SP3, Dual port block ram, coregen issue
  171. Spartan slave-parallel development board
  172. Symmetric clocks with ALTERA Quartus
  173. Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
  174. real constants in XST
  175. Sharing SDRAM on Stratix II DSP Development kit
  176. Using very large number in VHDL
  177. Altera mysupport
  178. Why some firmware is made by lattice's FPGA instead of C language?
  179. Verilog translation
  180. What is the diffrences between lattice's FPGA and Xilinx's FPGA
  181. Could you tell me some other good forums or website related?
  182. Kingston module structure
  183. USB Blaster
  184. Best FPGA for floating point performance
  185. PLL
  186. looking for OLD OLD software
  187. JOB: Sr. Hardware Design Engineer- FPGA/ASIC - PCB Design- Austin, TX
  188. Download bit stream onto ml310 ( virtex 2 pro ) using uart cable
  189. DDR memory writing all data twice & IPIF questions
  190. XST Help - Device Utilization Woes
  191. Two microblaze in EDK
  192. State Machine and BUFG
  193. [Q] Synthesis : HowTo Preserve FSM encodings
  194. Re: super fast divide-by-N
  195. Problem with quartus 5.0 sp1
  196. Modelsim on a remote display
  197. Xilinx ISE on remtoe Display
  198. Chipscope pro : timing constraint?
  199. Easy USB2.0 hi-speed device solutions ?
  200. FPGA-Based system design project
  201. Changing data into mapped register
  202. Evolutionary VHDL code example
  203. Antti's last comp.arch.fpga posting
  204. Altera NIOSII IDE problem???
  205. image sensor
  206. GSPx 2005 Conference
  207. XC5200 tool help needed
  208. Clock generation
  209. AHDL Abandoned in Quartus?
  210. 18-bit ROM in verilog
  211. How to disconnect a signal?
  212. Spartan-3 configuration -- peculiar problem
  213. VHDL Array indexing Issue in Modelsim
  214. XST (ISE 6.1i): Error: It's interesting and surprising
  215. Clock for serializer with a Spartan3
  216. Delay implementation and logic optimization.
  217. Modular design flow
  218. Avnet spartan3E development board
  219. Glitches in Output of FSM
  220. Creating EDIF from VHDL
  221. Peter Alfke's SPDT Switch Debouncer
  222. Troubles when mapping registers into microblaze address space
  223. EDK IPIF + User Core
  224. freeware/reasonable-ware c compiler for picoblaze
  225. Atmel AT40k/94k Configuration Format Documentation
  226. Xilinx ISE 6.3i on Gentoo Linux
  227. Regarding clock muxing
  228. high speed image capture
  229. Re: memory in verilog(its urgent plz help)
  230. Call for Delegates Communicating Process Architectures 2005 at Eindhoven
  231. Microblaze
  232. creating HARD MACROs broken in ISE 7.1 SP3 ?
  233. use of memory in verilog(uegent please)
  234. [Q] Virtex-IV with RLDRAM-II any experience with it?
  235. Clocks
  236. LatticeXP availability
  237. XILINX POWERPC <-> Embedded tri-mode-MAC connection
  238. rom
  239. Delays in verilog
  240. Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
  241. EDK and ISE questions
  242. ASIC suggestions
  243. Xilinx: Where has all the data gone?
  244. XBERT module.
  245. Using an oscillator in a rugged environment
  246. Cypress CY7B923/33 models
  247. Xilinx Forge compiler is discontinued ??
  248. FPGA Programming using Block Design Files or Graphic Design Files
  249. Rapid prototyping in FPGA
  250. Rapid prototyping in FPGA