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  1. 3rd party JTAG cables/controllers for Virtex-4
  2. Opal help please
  3. New Ethernet Development board, open-source
  4. PowerPC interrupt latency
  5. re:9bit vga with resistors.
  6. 9bit vga with resistors.
  7. ISE 7.1i installing issues on Windows XP Pro Sp2.
  8. Question about metastability that's been on my mind for a while
  9. Xilinx WebPack and command line
  10. Virtex4 shift register layout: Horizontal or vertical?
  11. FPGA behaviour when its used resource is >90% ?
  12. DDR constraints in Xilinx/UCF, Synplicity?
  13. Raggedstone1
  14. matrix inversion in hardware
  15. Xilinx PLB IPIF Master
  16. Verification using Chipscope
  17. Test
  18. Altera Gate Delay Simulation
  19. ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
  20. FSM with High load on clock signal
  21. Actel Libero upgrade - problem with clk pin - Synplify
  22. .lib file for Xilinx FPGAs?
  23. evaluation edk in Spartan-3 starter kit
  24. Xilinx ISE 7.1i file management
  25. Where to get informations about Virtex 4 FX Engineering Samples
  26. XMD and xilmfs help
  27. I'm desperate... EDK project simulation
  28. Systolic array architectures
  29. How to make XST understand to pack mux(A,B,A+B) in a single level?
  30. ise (lin64) and debian
  31. Radiation + CoolRunner2 CPLD?
  32. Xilinx IMPACT Problem... detects 101 unknown devices
  33. Altera NIOS PIO interrupt problem
  34. High Load
  35. Floating point multiplication on Spartan3 device
  36. Avoiding meta stability?
  37. Problems in simulating EDK system
  38. vhdl question
  39. New
  40. going backwards, Xilinx ISE 7.1 to ISE 6.3
  41. Weird problem in Xilinx WebPack ISE PACE 7.1SP4
  42. RLDRAM-II controller - Read problem
  43. Xilinx/Linux: sch2vhdl not working very hard
  44. for...generate loop with generics, constants (vhdl)
  45. Inferring design elements in ISE tool
  46. VHDL 2 dimension array
  47. Synthesis with Icarus Verilog
  48. More than one embedded system in ISE
  49. ISE does not initialize the bitstream of a EDK project
  50. ISE does not initialize the bitstream of a EDK project
  51. Virtex-4 FX20 PPC405 Startup Issue
  52. reading bits using JBits 3.0
  53. fixed point dot product with log2(n) pipe stages in vhdl
  54. Xilinx ISE 7.1i Portability Error
  55. Xilinx dev board with high quality video?
  56. PCB Software....
  57. I, Wish: I had an Spartan-3e NOW!
  58. Lattice XP availability
  59. Prevue - FPGA Dev Board Sale
  60. Testbench using Modelsim/VHDL - simple signal generation problem
  61. Power on reset generation in FPGA
  62. Spartan II, Platfrom Flash, ISE 7.1 - SERIOUS PROBLEM
  63. looking for 1 beta-tester for PLD2HDL (XPLA3 edition) tool
  64. Prob in Synthesizing and Simulating large Mux
  65. Help! I lost my life (Again)!
  66. Altera why so QUIET !?
  67. best SPI flash configuration solution for Xilinx FPGA's
  68. very urgent
  69. High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
  70. There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?
  71. Preloading SDRAM?
  72. CPLD program editing
  73. Altera SOPC testbenching in Modelsim?
  74. Synchronous & Asymchrnous Flip Flop Implementation
  75. ... failed to route using a CLK template
  76. Using LogicCORE on development board with Web ISE
  77. Turion 64 performance
  78. Electronic Component Spare Parts ....
  79. newbie questions: Xilinx vs. Altera tools and parts
  80. help needed
  81. Req to Xilinx: eCos port for Microblaze
  82. Pricing for V2-Pro / V4-FX ?
  83. Using 3rd Party FPGA flows and Xilinx
  84. FPGA : Decimation Filter
  85. 16-bit microprocessor dore for Actel
  86. Internal clock for apex20ke
  87. IPIF interface not fast enough
  88. Small C Compiler for Picoblaze
  89. a ISE installation problem on linux
  90. Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
  91. I am planning to purchase a Virtex-4 Eval board.
  92. Sythesis software for Virtex-4
  93. Spartan-3 starter kit and digilent jtag-usb cable
  94. Image Processing Algorithm based on FPGA?
  95. Any suggestions for prototyping in an ARM environment?
  96. How to run ngcbuild in windows xp environment?
  97. chipscope pro
  98. Spartan3E - problem in creating LVDS DDR pads
  99. vhdl state maching problem
  100. Xilinx XUP + Linux (firmware loading problem!)
  101. ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
  102. External dpram similar to blockram of Xilinx device
  103. lwip sockets on spartan 3 microblaze? Any examples?
  104. altera new bee
  105. Making timing assignment in Quartus
  106. Altera_VHDL_support library into Modelsim?
  107. question about creating RPM
  108. Cyclone on a shared configuration bus
  109. Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
  110. MAPLD 2005 Postings On-line
  111. "Free" core and license
  112. jbits
  113. Question on Metastability
  114. 10G serial port with no FEC?
  115. I need an Altera Excalib EPXA10 DDR Dev Board...anybody got one?
  116. 802.11g solution usable for FPGA design
  117. ML403 dcm phase shift reference design... anyone has a copy ?
  118. Linux USB XUP board
  119. Power Management for Xilinx and Altera FPGAs
  120. C-to-gates experiences
  121. Synchronizer Flip Flop / Metastability
  122. Need help in Flash simulation module.
  123. Need help in Flash simulation module.
  124. Announcement Free Symposium on the Future of Configurable Hardware
  125. downlaoding bit files to Xilinx FPGA
  126. Hints for efficient 32 bit multiplier
  127. Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...
  128. Network-on-Chip Architectures
  129. USB communication using PCI Logicore
  130. opb ip master/slave...arbiter problems
  131. Altera Programming Cables and EPCS16/64
  132. JBits query
  133. Xilinx Webpack Schematic
  134. data logging via JTAG?
  135. Xilinx Spartan-3
  136. Xilinx ModelSim VHDL Running Two Models
  137. Cyclone and NIOS II
  138. Output register instantiation in Quartus
  139. Count "1" bit in bit stream
  140. digilent USB2 module
  141. Xilinx ISE Passing IO pad attributes using UCF file.
  142. JTAG USB Circuit
  143. EDK libgen cc choice
  144. XST equivelent for Synplify "synthesis syn_preserve = 1"
  145. OPB bus communication
  146. Core import into ISE
  147. picoblaze IDE for Linux
  148. SoC embedded FPGA
  149. ISE 7.1i & Linux / reg code question
  150. Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
  151. problem with Thold violation under quartus
  152. program prom by the fpga
  153. xilinx ML310 board PCI DMA problem
  154. Simulation : EDK
  155. FPGA's in bulk and pricing
  156. Reprogramming FPGA over PCI???
  157. ISE 7.1i incremental synthesis
  158. Unknown price difference for xilinx fpga
  159. Two short-term research grants
  160. FPGA's in bulk and pricing
  161. Reverse Engineering Output Files
  162. Testbench failures for Opencores Ethernet mac
  163. modelsim
  164. Modelsim XE, what's the latest version?
  165. Using two PowerPCs
  166. Generating Modelsim Verilog resource libraries - pointers/questions
  167. [PATCH] Xilinx Linux driver package clean-up.
  168. Dll device for FPGA
  169. Using BRAMs in VHDL on Virtex II FPGAs
  170. Xilinx Wizard does not create vhdl DMA template?
  171. Insight / Xilinx Spartan II Demo Board files?
  172. Software tools for architectural diagrams and for timing diagram entry?
  173. Digilent USB2 module in B1 expansion slot
  174. how to set OPB EMC for flash use?
  175. Looking for info on the V8/Arclite MicroRISC 8-bit core
  176. DEV_CLRn and CRC_ERROR on ALTERA Cyclone
  177. Re: Xilinx ML403
  178. re:SDRAM HOW?
  179. Interrupt Handling
  180. problem with programming avnet edk board over LPT
  181. DCM question
  182. ISE 7.1 on Linux, ngdbuild failed without error
  183. Version Control Software
  184. Re: SDRAM HOW?
  185. Re: SDRAM HOW?
  186. ISE 7.1 service packs
  187. HAL fuse map organization issue
  188. Matched Filter
  189. PCI configuration questions.
  190. IP Protection of code block in Xilinx FPGA?
  191. Looking for a DIgital Systems book with JPEG example code
  192. VHDL: Address Decoder
  193. USB tranciever + controller in FPGA
  194. TAP controller
  195. FFT implementation in Xilinx Spartan 3 started kit
  196. ARM IP Core implementation in FPGA
  197. fan out capability of FPGA
  198. XilinX MAC FIR
  199. Is a CPLD appropriate for this triple PWM application?
  200. edk service pack download
  201. FIFO design using Virtex-II block ram..
  202. Spartan-3 1000 -5 availability
  203. floppycontroller
  204. 24 Counters on one board
  205. Migration Altera APEX20KE to ???
  206. Tree Representation of Logic Circuits
  207. CPU benchmark for Xilinx PAR
  208. P&R speed higher than synthesis
  209. FFT implementation in Xilinx's Spartan 3
  210. Please Help:Modelsim-Altera License "Verilog Computer Based training course"
  211. Microblaze & Memory DMA operation
  212. ISE 7.1i & Linux / reg code question
  213. reducing the number of IOBS in a design
  214. modelsim simulation problem
  215. Xilkernel problem
  216. xilinx ise / update schematics
  217. place and route
  218. Fatal errror in ISE 6.3 i
  219. SDRAM quality
  220. several ucf files?
  221. Block RAM problem (spartan 3)
  222. Which JTAG cable for Xilinx & Linux?
  223. future of antifuse fpgas?
  224. creating a custom opb bus master
  225. Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
  226. compedklib error
  227. implementing the tristate bus
  228. Has anyone successfully used opencores PCI in FPGA desings?
  229. Post synthesis simulation errors
  230. Reading a PAL fusemap with a microscope
  231. Timing Violation Quartus "__Z" issue
  232. EDK 7.1 simulation
  233. Microblaze and LMB
  234. digilent web site?
  235. Quartus II - Timing Analyzer
  236. xilinx virtex 2 multimedia board ( XC2V2000)
  237. [XST] FSM extraction question
  238. ML361 Documentation....
  239. burn xcf16p through PCI jtag
  240. pll
  241. Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
  242. RocketIO code example
  243. ISE7.1 SP4: proble and chipscope problem
  244. chipscope/core implementation
  245. ISE 64bit question
  246. used boards? cache design? DDR2 controller?
  247. Help finding Signetics Datasheets
  248. OpenTech open source designs and tools
  249. to use flash on the fpga board
  250. Signed addition