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  1. fastest possible USB
  2. Clock signal for an external peripheral
  3. SDRAM controller.
  4. Is this even true???
  5. Signal timing problem
  6. Can't pack into OLOGIC
  7. open-sourced FPGA (vhdl, verilog, C variants) design libraries, workingtoward a GNU (for hardware) paradigm
  8. fpga speed logic/density MIPS/FLOPS as compared to general purposemicroprocessors
  9. Looking for tutorials for bootloader writing on xilinx SOC ??
  10. Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
  11. Coolrunner output pins stuck at 0V
  12. Spartan 3e is slower than Virtex 2p
  13. In Xilinx, how do I delay a signal by a fraction of a clock cycle?
  14. Rocket IO reset problem
  15. Xilinx Block RAM - initializing with Intel Hex-File
  16. Best Case Timing Parameters
  17. How do i detect ethernet frames of layer 2 using ethereal?
  18. Multilinx, where do I get 3.3V power?
  19. EDK 7.1, Virtex4 GPIO PULLIP problem
  20. Forcing carry-ripple adder ?
  21. Installing FPGA Advantage on Linux machine
  22. how to implement Fast Fourier Transform on virtex pro
  23. pci ml310 board
  24. ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
  25. Wirelength information from Xilinx ISE 6.1
  26. Need some help with interfacing spartan III to a computer...
  27. What are important factors when selecting Intellectual Property?
  28. Bus for Spartan3
  29. old xilinx components
  30. Internal signal to drive clock resources
  31. 8x8-bit multiply
  32. how to use registers and fifo in ipif
  33. What does the IP in IPCORE stand for?
  34. PC Core AD(x) I/O Enable?
  35. To create an IPCORE
  36. Suggestions/Recommendations with CPLD's and Software
  37. Delay insertion in Xilinx Verilog
  38. Easy Xilinx Platform Studio Question
  39. looking for FPGA pin header board
  40. ISE 8.1 news--Ba*** going away, but WebPack gains devices and features
  41. Verilog Editor.
  42. ML402 DDR SDRAM
  43. XILINX ISE 7.1 Symbol Editor
  44. What does @ mean in EDIF?
  45. how to map kernel element of FFT to VIRTEX Pro Board
  46. VHDL algorithm/code for implementing QAM on FPGA
  47. BRAMs readback
  48. Xilinx Package/Logic Options
  49. Malloc on PowerPC on VirtexII pro
  50. Spartan3 bus for DSP
  51. PCI test bench
  52. which Altera CPLD?
  53. Adder synthesis
  54. The Xilinx MultiPoint Synthesis Flow - Synplify Pro
  55. xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
  56. Font requirements for patent applications
  57. USB host
  58. Why Spartan-3e is the best
  59. Anybody understand this ISE 7.1 error, and what to do about it???
  60. icarus verilog
  61. ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK)
  62. Clock J4
  63. use ppc405 on virtex-II pro
  64. Actel SoftARM IP core generator tools finally available !!!
  65. Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!
  66. I have received a job offer
  67. XC2VP125
  68. Using inout ports in VHDL
  69. LWIP on microblaze socket limit to 2
  70. using Spartan3 DCM in ActiveHDL
  71. Xilinx trouble opening ml40x_emb_ref_xx
  72. crc code using vhdl found , few questions on it!!!
  73. FPGA : PCI core needed
  74. Re: FPGA : PCI core needed
  75. Re: FPGA : PCI core needed
  76. Re: FPGA : PCI core needed
  77. Newbie. Clocks.
  78. clock detection
  79. FPGA C Compiler on sourceforge.net (TMCC derivative)
  80. ChipScope on ML401 kit
  81. differential clock in EDK
  82. FPGA : PCI-CORE
  83. Spartan IIE VHDL inout port bidirectional bus problem.
  84. Lead To Lead Free ROHS help?
  85. can ethereal detect an ethernet packet for which crc is wrong
  86. Virtex4 temperature-sensing feature... does it work?
  87. Xilinx V2P Speed Grades
  88. Thank-you Xilinx!
  89. Simulating Cyclone II PLL
  90. Xilinx ML403 Error 1 LED
  91. question on sw tools for xilnx FPGA
  92. Quartus II Simulation
  93. Integrator
  94. [xst]:clk information question
  95. Memory usage and ISE
  96. SystemACE parts wanted
  97. array type implementable in ISE?
  98. Why are there two patents with same title
  99. Spartan3 DFS & DLL Behaviour
  100. ISE 8.1, EDK 8.1 any pre-release info available?
  101. Xilinx ML403 Virtex 4 IIC uses bitbang test?
  102. Semi-OT: LVDS and Cold Sparing
  103. Spartan-3E starter kit
  104. How to reduse the logic.
  105. xilinx design reuse netlist format
  106. Xilinx Microblaze prefill icache
  107. Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)
  108. Reed Solomon generation / verification
  109. Virtex-4 DSP48 - special features (Peter Alfke?)
  110. ethernet phy- DP83847
  111. Mitrion-C
  112. Sigma-Delta A/D
  113. hex rep. in VHDL
  114. locking hdl to a particular fpga
  115. another FPGA/asic vendor dead :(
  116. Coregen Memory Initialization issue
  117. Single Event Upset
  118. ASIC HDL coding styles
  119. ASIC HDL coding styles
  120. HDL coding styles
  121. Cost to go from FPGA to ASIC
  122. Anyone know hwicap?
  123. Xi ISE 7.1 ModelSim
  124. Optimizing a State Machine
  125. crc on only data or including the address
  126. state machine with 2 clock's
  127. Condition Coverage Using ModelSim
  128. SDRAM in EDK
  129. Physical interface for PCI express(PIPE) electrical information
  130. cic filter
  131. newbie question
  132. 7.1i on Linux installation saga
  133. ETHERNET MAC
  134. Anyone have experience with Linux in V2Pro?
  135. EDK custom IP read/write
  136. Xilinx FIFO Generator: FIFO Length
  137. xpower : logic power=0
  138. OSD implementation in FPGA
  139. System ACE equivalent for CPLDs
  140. Xilinx ISERDES
  141. Xilinx ML403 Many warnings
  142. a few questions
  143. verilog code
  144. XC3S4000 pricing?
  145. Doubt in using CD22M3494
  146. 24 to 32 8-bit PWM outputs
  147. SoC Processor design at gate level for edu
  148. RS232 Uart for Virtex-II Pro
  149. FPGA Design Docs
  150. write on a DG834GT modem
  151. clock frequency after RTL synthesis vs PAR
  152. .dat to .bit
  153. Internal Loading in Spartan3
  154. Coregen Memory Initialization (.coe file format)
  155. RISC pipelining question
  156. netgen port renaming
  157. ML401
  158. low power design and unused i/os
  159. "Cannot synthesize logic..." ERROR
  160. RPM reference for xilinx
  161. Avnet Technical Support Terrible!!!
  162. EDK on Virtex4 FX using embedded ethernet MAC
  163. C source for Spartan-3 with microblaze soft core for RS-232 comm
  164. EDK/ISE : unroutable design
  165. to write the driver for my own ip core
  166. MAC Architectures
  167. Spartn 3 configuration failure
  168. dagen.exe,where can i get it,thanks(for digital filter)
  169. which is Low power FPGA?
  170. Implementation of 1024 point FFT in Actel FPGA
  171. How to speed up the critical path (Xilinx)
  172. WANTED: Contract Verilog Designer
  173. Webpack install yields "299" error
  174. Xilinx USB cable
  175. LSI RapidChip
  176. gast division carry chain usage
  177. Anyone used the Xilinx' floating point core?
  178. Carry Chain Design
  179. Simple PWM Spartan 3
  180. Newbie question: XC3S400 Gate Count
  181. Program FPGA from PowerPC in V2P
  182. clock timing
  183. FPGA timming
  184. Data2Mem usage - help required
  185. Rosetta Results
  186. using i2c core
  187. XChecker cable and chipscope
  188. chipscope pro problem
  189. ADC implementation on fpga? Information and procudures wanted.
  190. LSI RAPIDCHIP
  191. Error (XST): translate terminal to FCT
  192. Low-cost, high-quality design team
  193. Best Async FIFO Implementation
  194. Implementing I2C master
  195. About with Synplify Pro?
  196. Mixed voltage in JTAG chain.
  197. 3.3v<->5V
  198. Problem with Xilinx Impact under windowsXP
  199. Implementing five stage pipeline
  200. Problem with Xilinx Impact under windowsXP
  201. CPLD design software under WINE?
  202. CPLD design software under WINE?
  203. xilinx fpga beginner question
  204. Synplify Pro and automatic Retiming/Pipelining
  205. Help me
  206. Ciappla
  207. FPGA : PCI core needed
  208. Linux and Platform USB Cable
  209. Xilinx ML403 Board Beginner
  210. Re: Distributed microcontroller computing
  211. Anyone remember the really early Xilinx FPGAs?
  212. Xilinx EDK : mb-gcc linker errors with C++ features
  213. Storing a file onto FPGA
  214. IO interface standard of fpga
  215. Data width change in opencores Ethernet MAC
  216. Simulink to hdl conversion
  217. IOs on ML-310 Evaluation Board
  218. RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
  219. IDELAYCTRL floorplanner/fpga editor/pace problem
  220. NgdBuild:455, Ngd:Build:924 when using MGT XBERT
  221. User Library in ISE
  222. how to implement 8x8 circular shifter on FPGA
  223. Question regarding FPGA startup ROMs
  224. stratix fpga pll
  225. How to Reduce Interconnects (VDD and VSS)
  226. question: timing constraint for clock enable
  227. PCIXCAP
  228. LUT 4:1 VS FF
  229. ModelSim XE: Can't import vital 2000 library
  230. Problems with phase shift dcm
  231. converting 12v signal to 3.3v
  232. iVerilog / VVP output to GTKwave.
  233. Compiling Altera LPM FIFO into Modelsim Error
  234. 64 bit processor for FPGA workstation?
  235. What is a "full custom" design?
  236. Xilinx Chipscope VIO Core Utilization
  237. Eliminates meta stability (yes or no)?
  238. Verilog VPI
  239. Using the BSCAN primitives
  240. Xilinx IPIF PLB Master Update
  241. How many decoupling capacitors need on one device?
  242. Questions on DCI split termination of spartan-3
  243. Clock routing
  244. systemc to verilog translator v0.5
  245. VHDL : Use concatenation on port mapping
  246. Yet another NGDBUILD 455 problem
  247. Vector, Signal and Image Processing Library
  248. 16550 VHDL code
  249. Bus master DMA and cache coherency
  250. Library Simprim cannot be found?