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  1. IP2IP_Addr in IPIF
  2. Source address in IPIC
  3. Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
  4. Microblaze question
  5. Call For Papers: June 26-29, WORLDCOMP'06 (28 joint conferences in CS, CE, and applied computing), USA
  6. Modelsim error when doing: port map(a => not(b))
  7. AC97 Controller
  8. high input to CPLD
  9. Mixing and matching related clocks question.
  10. How will synthesizers handle these statements?
  11. BGA central ground matrix
  12. Lattice Semiconductor, Lattice Forums Go Live
  13. PLB DDR Controller : Sl_rearbitrate issue
  14. don't care condition
  15. xilinx linux source?
  16. Spartan3 pullups
  17. microblaze GNU tools for win32 binaries (from 8.1 build) for download
  18. Strange problem with sysace + linux + Ace on SanDisk.
  19. ISE 8.1.01i does not implement new BUS macro
  20. Maximum system frequency on FPGA/CPLD
  21. BPSK modulation on Xilinx FPGA
  22. LDPC
  23. Quartus Fitter Warning
  24. Gbit technology selection?
  25. Die Area
  26. For our Study We need STM1, 4 , 16 Block diagram where to get it
  27. Parallel Cable IV does not work with parallel to usb cable
  28. Ethernet : MAC vs PHY
  29. Back to max thermal and power for XC4VLX200's
  30. Wanted Help on All Digital PLL
  31. Wanted Help on Aall Digital PLL
  32. scrambling
  33. ERROR message when programming FPGA with Altium Designer 2004
  34. Constraining a 50 MSPS DAC Interface
  35. URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM
  36. Interactive Logic software now available for download
  37. Get Rich
  38. a question: task, function vs module
  39. power up reset question
  40. Analog FPGA Project -- VIdeo Router
  41. Open source access to generate netlists into Altera tools? Others?
  42. Xilinx Legal
  43. TI Technical screening phone interview
  44. Floating-Point Unit (for JOP)
  45. Virtex4 : Audio Codec AC97 LM4550
  46. starting MacroBlaze development
  47. Remotely updating Altera FPGA configuration
  48. Call for Papers: IMECS 2006 (international multiconference of 14 engineering & computer science conferences)
  49. Acquiring video frames and processing pixels in Xilinx
  50. Competition to win Raggedstone1 RS1-1500 Spartan-3 FPGA Board
  51. 32 bit processor ? Open IP-Core
  52. XPower- Advanced power report
  53. XDL Tools wiki site
  54. Serial flash configuration with "Xilinx platform cable USB"
  55. -tC ***Hot stuff - check this out !!! -tC
  56. Digilent FPGA & Handel-C
  57. Connection between FSL and XCL
  58. Debugging Spartan3 slave serial configuration
  59. Lattice high end FPGAs to be announced soon
  60. HOW CAN I USE OPB EMC
  61. Virtex-4 ISERDES and ADS527X ADCs
  62. EDK 8.1 ... delay
  63. XilNet server data streaming problem from PPC
  64. LogiBlox on Foundation 4.1 Error
  65. Impact 8.1 problems with non xilinx device in chain
  66. C to FPGA Tools (Impulse C and others) and necessary trig IP
  67. tristate to logic conversion
  68. Multichannel Opb Memory Controller question
  69. Xilinx OBUF attributes on Spartan3
  70. Are the Xilinx pcores files not searchable?
  71. PPC Memory Management
  72. Current to sink PROG_B low?
  73. So Xilinx, is XDL and related libraries an available open source interface?
  74. Microblaze data cache question
  75. DDR2 SDRAM controller
  76. SDRAM Controller
  77. SDRAM Controller
  78. ISVLSI 2006 - Call for Participation
  79. Stop. Go. Yield.
  80. Very very OT but Floating Point FPU +> current news murder story
  81. Xilinx on the fifo16 issue
  82. Flex8000 / MAX+plus II 10.2 / license from altera.com
  83. XO for Xilinx V2Pro MGTs
  84. Call for Papers: FECS'06 (part of WORLDCOMP'06)
  85. Spartan3 DC datasheet
  86. Spartan-3 Starter Board
  87. CFP: 2006 MAPLD International Conference
  88. open source fpga programmer programs
  89. How to generate ILA with ChipScope pro in Linux
  90. So what happened to JHDLBits?
  91. encryption
  92. porting linux on ml403
  93. custom ip using EDK
  94. How to handle the "gate count" issue?
  95. testbench.tdo file Xilinx ISE 7.1
  96. undefined reference to `xilkernel_main'
  97. Verilog tutorial by John Sanguinetti
  98. Newbie: xilinx vs arm
  99. rocket IOs with web pack
  100. problem to synthetize with ISE
  101. help:dual-edge flip-flop possible using Verilog?
  102. LVDS Input buffer in VHDL (ISE)
  103. obtaining ABEL code from schematics source in a design with ISE Webpack ?
  104. FPGA board with High Speed LVDS
  105. Virtex-4 BiDirectional Ports
  106. Xilinx ISE & StateCad
  107. RPM.
  108. Configuration Spartan 3
  109. SSOs and Vcco on Spartan3
  110. Reconfigurable Array of Array
  111. CFP: IAENG International Workshop on Computer Science (in IMECS 2006)
  112. Webpack 8.1i size
  113. Starting with LVDS
  114. The attributes specified to DCM instance doesnot get written to the .vm file
  115. self repairing FPGA s !?
  116. Third Call for Papers to JCRA 2006
  117. PicoLA: FPGA based logic analyzer
  118. post-fit simulation failed
  119. ISE Ba*** customers
  120. FPGA-Programmable power supply
  121. FPGA-Programmable power supply
  122. Xilinx Partial Reconfiguration add-on module
  123. CFP: International MultiConference of Engineers and Computer Scientists IMECS 2006
  124. EDK 8.1, Finally!
  125. Virtual Pin in Xilinx ISE
  126. Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
  127. Irrelevant, stupid, racist, and worse.
  128. Creating Multiple Configuration PROM File
  129. Modelsim problem
  130. need for a group FAQ?
  131. Timing impossible to meet; PAR stops.
  132. Reading user data from PROM
  133. First Impressions of Actel Fusion?
  134. Actel Fusion
  135. Stratix-II <==> Virtex4 interconnect; 10 GB Ethernet cores
  136. Matching the UCF files from MIG and ML403 turtoial demo
  137. Matching of the UCF files from MIG and ML403 turtoial demo
  138. Virtex II Pro-X Rocket I/O problems
  139. Is there someone have the ata controller?
  140. VHDL Bus Macro for V2Pro
  141. Security of Xilinx Virtex2 Pro
  142. How in Design Compiler disable writing out "Assign" statement into the netlist?
  143. Sorting large amounts of floats
  144. Loading Data from Prom
  145. OT:Shooting Ourselves in the Foot
  146. Constellation symbol to bit's soft-probability?
  147. Xilinx DDR SDRAM for ML40x
  148. Strange Q1 Output on Xilinx V-4 ISERDES
  149. Quadrature Encoder ::
  150. Bogus Hold Violations with 2X clock on Xilinx ISE 7.1
  151. V4 not packing registers into IOBs
  152. Xilinx padding LC numbers, how do you feel about it?
  153. DDR Memory Access Interfact by Virtex-4 FX12
  154. Disabling cross domain checking for Xilinx ISE
  155. profiling with virtex4 powerpc
  156. PCI arbiter (doubt in REQ signal)
  157. How much do you trust your CAD Program?
  158. How to NON_CLK pin that messes my clock
  159. data2bram and coregen
  160. EDK 8.1
  161. where to find the bfm files?
  162. FPGA interface to FLASH
  163. clock generation with DOPPLER shift
  164. ISE8.1 on Linux, first impressions
  165. xilmfs on flash
  166. Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??
  167. Call for Papers: ICWN'06 (part of WORLDCOMP'06)
  168. Selling Microblaze based Machines
  169. Call for Papers: RTCOMP'06 (part of WORLDCOMP'06)
  170. Data2Mem with CRC for Virtex FPGAs
  171. TL16C550CIFN
  172. Raggedstone specifications ...
  173. [RANT] Webpack 8.1 editor totally messed up ?
  174. Standards in the real world: UWB
  175. Xilinx Virtex-4 RAMB16
  176. Spartan3 initialization with DSP
  177. How to set Xilinx compiling parameters to get PCI setup time right
  178. CPLD serial buffer problem
  179. xilinx free Sample Pack info now also on Xilinx own webpages
  180. Unassigned pins
  181. Call for Papers: PSC'06 (part of WORLDCOMP'06)
  182. Virtex 4 : Configuration-memory readback
  183. S3e slower than S3
  184. FIFO in SDRAM
  185. PCI arbiter doubt
  186. OT: BGA chip test sockets for sale
  187. Getting Gate Counts from Quartus
  188. Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
  189. Migrating Project from Xilinx ISE 4.1 to 8.1?
  190. BRAM/XMD strangeness?
  191. Xilinx HW-SPAR3_CPLD-DK kit
  192. How to drive 4 output ports with one combinational signal
  193. ATA controller in fpga
  194. NIOS II fmax on a Cyclone
  195. problem with the SRAM
  196. programming devices using other tools
  197. New PCI extender
  198. Call for Papers: CDES'06 (part of WORLDCOMP'06)
  199. Mistake in Xilinx dsp-book.pdf?
  200. Call for Papers: PDPTA'06 (part of WORLDCOMP'06)
  201. Student Pricing Now on our Website
  202. Student Pricing Now on our Website
  203. Any FPGA with programming info available?
  204. what happens in SDR-SDRAM if i exceed tRAS(max)
  205. how do I minimize the logic in this function?
  206. FPGA Altair Advice
  207. Xilinx Virtex-4 BRAM-16 Simulation
  208. Xilinx ISE 8.i Editor
  209. Directed routing in Xilinx V2PRO.
  210. WebPack 8.1 report viewing
  211. bandpass filter design for ACTEL FPGA
  212. PCI e clocking
  213. Xilinx 8.i and ML402
  214. OT: RoHS and Lead?
  215. FPGA Journal Article
  216. boundary scan of altera epm570F
  217. Xilinx simullation error
  218. Call for Papers: CIC'06 (part of WORLDCOMP'06)
  219. Xilinx Vertex II Pro with tow VDEC videodevices
  220. Newbe Startup Time Question
  221. How to create a delay BUF?
  222. Conflicts between ISE4.2 and win2000 SP4
  223. Dev board prices going up?
  224. DSP soft processors
  225. virtex-ii pro linux partition check hangs
  226. Active Silicon Frame Grabber and IMPACT ...
  227. Special Issue of Journal of Systems Architecture, Elsevier
  228. Webpack 8.1 device support
  229. UCF-File problem
  230. PLX PCI9656
  231. best evm for virtex-4 and linux
  232. Verilog Code for echo on Serial Port
  233. Samples
  234. SDRAM Clock Skew
  235. FPGA and video generation
  236. IEEE/NASA Conf on Adap. HW
  237. Xilinx Spartan3E Sample Pack 3rd party programing support now available
  238. Will ISE 8.1 work together with EDK 7.1?
  239. Software- to- PCI design communication.
  240. Xilinx 7.1 ISE ModelSim input files
  241. International Symposium on FPGAs -- Call for Participation
  242. application running on the top of Linux on virtex-ii pro
  243. Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
  244. Xilinx Routing & Clock/Data Skew
  245. Altera MAX-II: User logic access to USERCODE_REGISTER?
  246. FPGA configuration time for PCI identification ?
  247. ISE 8.1i WebPack available
  248. Seminar Reminder (UK)
  249. ISE 8.1i WebPack available
  250. Breaking of Ethernet Frames