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  1. implement IP TCP Layer in FPGA
  2. a master-IPIF problem on the PLB bus
  3. The 95108 cpld is getting heated when connected by CRO
  4. PPC405 - FPGA interface design
  5. Need a SPI 4?
  6. USB 2.0 OTG in FPGA
  7. configuring Hardware
  8. ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
  9. Raggedstone1 - New Worldwide postage
  10. Variables in VHDL and simulation
  11. using evaluated ip core with edk 7.1 i
  12. How to use a .coe file for rom/ram in system generator
  13. From ASM to verilog Code
  14. 8051 IP core with JTAG debugger for FPGA?
  15. Spartan3 decoupling
  16. High Speed Development Board
  17. need byteblaster II source code
  18. project validation: best procedures?
  19. altera max 7128s blanking
  20. System with multiple buses
  21. ARCnet interface gate count
  22. DDR2 Memory Design: Layout, timing
  23. virtex 4
  24. Combinatorial Division?
  25. OpenRisc 1200 on Spartan 3 - problems with stability and enablingcache
  26. Truth about Spartan-3E DCM speed
  27. Kalman filters
  28. query!! need help!!
  29. Input stage for VHF frequency counter in an FPGA?
  30. Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
  31. JTAG problem
  32. FPGA to ASIC migrate
  33. Ray Andraka's Book?
  34. state machine and i2c
  35. PowerPC based SoC design, getting it working from first attempt
  36. configuring stratix GX Fpga
  37. doubt
  38. RC1000pp with XCV400
  39. Virtex-4 Output Primitive
  40. Cannot use ML310 DDR
  41. Layer 2 (MAC) Research Project to Eliminate Routers
  42. Xilinx ISE 6.3 confusion with CPLD logic results
  43. How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
  44. bypass between ilogic and ologic
  45. Relative placement constraints in Xilinx ISE w/ Verilog
  46. Virtex2: can I really just leave M1,M2,M3 pins floating?
  47. fix: Xilinx USB Platform Cable on linux 2.6
  48. How to use Gigabit transciever
  49. EDK 8.1 SP1 released, DDR2 support is now included !!
  50. DSP
  51. SMSC 91c111 and LwIP
  52. Xilinx Spartan 3 SSO guidelines for CP132 package?
  53. "par.exe" halted without error (partial configuratio)
  54. FPGA work - San Diego area
  55. arctangent again
  56. EDK -running from external sram
  57. Any one worked with Digilent Adept(transport) feature??
  58. JHDL Application
  59. SDRAM Reading problem
  60. Xilinx 8.1.02i map failure
  61. Is FPGA code called firmware?
  62. Quartus Tcl interface
  63. Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
  64. PPC LUT inputs/outputs
  65. DVI - LVDS controller
  66. multiphase data extraction question
  67. Problem with multple clcok domains
  68. Parameterized Comparator Verilog Code
  69. Inferring Adder with Carry In and Cary out
  70. FPGA - software or hardware?
  71. FPGA Board Competition
  72. help with VGA timings
  73. Addressing BRAM in a V2 pro
  74. FPT'06: First Call-for-paper
  75. Did anyone doing research on power electronics control using FPGA?
  76. What is the best price you have gotten on for these FPGAs?
  77. MontaVista Linux and Virtex-II & 4
  78. Xilinx ISE Simulator Arrays
  79. Approximate power and area values for a 1-bit SRAM cell.
  80. PC104+ Card
  81. Xilinx System Generator Black Box
  82. Xilinx HardMacro "configurable" ?
  83. Xilinx development board
  84. using ISE and GNU tools for Xilinx V2Pro/V4FX PowerPC
  85. Xilinx development board
  86. Find and fix critical paths in gate level netlist by GOF
  87. ISE Simulator Price
  88. open position: developing high-level FPGA programming tools
  89. DDR SDRAM Controller
  90. low level ethernet interface driver
  91. DDR SDRAM Controller
  92. equivalent time sampling
  93. Xilinx UCF area constraints disappearing
  94. Memory initialization for synthesis in ISE
  95. Poll: what's would your requirments be for ESL (Electronic System Level) flows?
  96. Communication between FPGA and PC with ethernet
  97. Xilinx Tight packing : Map error, the tools don't get it ...
  98. Standby current measurement
  99. sdram modeling
  100. [Handel-C]Interface with C
  101. [Handel-C]Interface with C
  102. VHDL simulation
  103. Maxim anounce MAX3421E SPI-USB Host/Peri
  104. opencores.org ?
  105. Xilinx EDK GPIO: Can I drive internal logic with it?
  106. WIFI Compact Flash
  107. Need some Advice, please
  108. User masks in HardCopy and HardCopy II
  109. Implementing a two-modulus PLL divider in Altera Stratix II
  110. VHDL or verilog
  111. ISVLSI 2006 - Call for Participation
  112. DDR SDRAM Controller
  113. pci express ac coupling
  114. delay using integrator
  115. EDl Lab
  116. WebPACK license (and Quartus Web Edition too).
  117. CPLD-SPI_flash configuration system problem.
  118. What is 1QN and 2QN in Xilinx CORDIC ?
  119. system generator : change the default parameters
  120. DIFF_OUT buffer example
  121. system generator : interrupt with FSL
  122. Altera Stratix EP1S80 DSP Development Board Non-Volatile Configuration
  123. EDK Woes and Worries
  124. DDR SDRAM on ML401
  125. News from Embedded World in Nurnber
  126. can i use gcc of EDK?
  127. What is back_annotate?
  128. Xilinx EDK BRAM confusion
  129. EDK: OPB Question
  130. Re: Problem of Initial Value in VHDL code
  131. Xilinx HDLParsers:810 or HDLParsers:3329
  132. dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
  133. 8.1i SP2 download problems
  134. is there a way to initialize signals to a value
  135. XPower report precision
  136. Which SelectIO for FPGA <-> FPGA buses?
  137. ModelSim Licence problem
  138. ModelSim License Problem
  139. Block vs. Distributed RAMs
  140. Dual Port Block RAM Inference
  141. Entity with Multiple Architectures
  142. I2C and posedge sampling
  143. Problem programming Altera flex 10k100 & EPC2
  144. EDK Simulation
  145. microblaze with FSL
  146. "does not fanout" warnings with inouts
  147. Altera RoHS Irony
  148. SCHEMATICS ... Is anybody as frustrated as I am with the software?
  149. Question about using LMB to connect BRAM in MicroBlaze
  150. Rocketio, modelsim xe
  151. spartan-3e starter kit
  152. xilinx ise 8.1 mig 1.4 /1.5
  153. ISVLSI 2006 - Call for Participation
  154. [ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded
  155. How to decode FAR register in Virtex-4?
  156. Newb question about Xilinx Impact and parallel cable III ....
  157. PacoBlaze updated
  158. Xilinx + I2C + PPC -> crash
  159. digital logic library by 74xxxx part number?
  160. spartan3 starter kit.
  161. Spartan3 configuration
  162. schematic capture
  163. Simulation problem using CONV_INTEGER
  164. using FPGA in control field
  165. which one among the available FPGAs is best for a fresher?
  166. LVDS
  167. Creating low freq. clock on Altera FPGA
  168. Using Ethernet to control/initialize FPGA
  169. Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
  170. SMP on virtex-ii pro
  171. SHARCS 2006
  172. Spartan-3 Serial LVDS max speed?
  173. Altera EPLD
  174. ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!
  175. Spartan3 embedded synchronous multipliers
  176. Simulation of MicroBlaze embedded system
  177. ModelSim # Error loading design
  178. Xilinx ISERDES Q1 issues
  179. Lattice new ECP2 parts
  180. Need help with generating video patterns using VHDL
  181. Lattice high-end devices announced after years of rumours...
  182. OPB busmaster device
  183. EDK - PLB/OPB Bus questions.
  184. EDK - PLB/OPB Bus questions.
  185. Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
  186. Which workstation or server should I take to build a state-of-the-artFPGA CAE tool workstation?
  187. Async Processors
  188. Virtex4 Powerdown, Vcco questions
  189. vhdl to edif
  190. MicroBlaze in Spartan 3 playing tuxchess :)
  191. Open Verification Libiary Free Download
  192. How to gnerate VCD file with hex outputs.
  193. ISVLSI 2006 - Call for Participation
  194. DK: Interfacing Handel C and VHDL
  195. I2C timing problem
  196. ISE Simulator
  197. Looking for information on SGRAM and GDDR
  198. Spartan3 Live Insertion with XC9572XL chip
  199. latest XILINX WebPack is totally broken
  200. Microblaze Virtual platform problem
  201. why does speed grade effect VHDL program??
  202. input signals in ISE simulator
  203. Software reset for the MicroBlaze
  204. Microblaze using SPI flash as instruction memory
  205. Xilinx Spartan 3 LVDS Misbehaving
  206. Call for Papers: CDES'06 (part of WORLDCOMP'06)
  207. Great Job Board
  208. doubt
  209. Re: please let me know what hardware is generated for this piece of verilog code
  210. Call for Papers: CIC'06 (part of WORLDCOMP'06)
  211. nios II stratix II handling interrrupts from uController
  212. cheap USB analyzer based on FPGA
  213. clock problem --I new to this field so if question is silly don't mind
  214. Verilog 2's Complement Shifter
  215. A great onestop spot
  216. Software Defined Radio Transmitter Demo Board
  217. Arbiter for several wires competing
  218. microblaze xmd question..
  219. Xilinx MIG
  220. Xilinx Pci Express core and Nital board Issue
  221. realize pci in fpga
  222. Call for Papers: PDPTA'06 (part of WORLDCOMP'06)
  223. ISVLSI 2006 - Call for Participation
  224. hprep crash with ISE 8.1i, service pack1
  225. Tefzel or Kynar for PCB mods ?
  226. VGA and framebuffer interface (Waste of BlockRAM)
  227. Call for Papers: GCA'06 (part of WORLDCOMP'06)
  228. RocketIO & Infiniband BERs?
  229. Protected power calculation spread sheets
  230. usb gadgets and xilinx
  231. NMEA Decoder/Display
  232. Call for Papers: ICWN'06 (part of WORLDCOMP'06)
  233. handle-c and xilinx
  234. High-density logic with simple, documented architecture ?
  235. multi-processor linux on xilinx
  236. Xilinx compxlib error using VCS
  237. advanced vhdl lerning
  238. core generator
  239. fpga hardware "breakpoint"
  240. Looking for literature on microprogrammed machines
  241. why such fast placement?
  242. quartus and VHDL/Verilog libraries
  243. Quartus programmer problem
  244. question for the EDK users out there...
  245. [map error] unable to pack a IBUF into the IOB
  246. Xilinx: generic tristates and multiplexers
  247. FPGA ogg Vorbis/Theora player
  248. FPGA growth vs. ASIC growth
  249. I need your process pictures
  250. I need your process pictures