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  1. Microblaze to My IP-Core connection
  2. FATAL_ERROR while creating a test bench waveform (ISE WebPack 8.1.01i)
  3. Fixed vs Float ?
  4. PacoBlaze with multiply and 16-bit add/sub instructions
  5. ignore thread
  6. Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
  7. DDS
  8. SMTP
  9. Looking for a V4FX development board
  10. What are the major difference between MXE 6.0 and MXE 5.7?
  11. Free Manpower Recruitment Service for Recent Graduate FPGA Engineers Visit www.fpgasps.com
  12. VHDL LUT
  13. Start Your Free Blog
  14. is conv_integer(unsigned(value)) synthesizable
  15. FPGA FIR advice
  16. memories for virtex-4 and Spartan-3E
  17. Free Manpower Recruitment Service for Recent Graduate FPGA Engineers Visit www.fpgasps.com
  18. Free Receuitment Service for Recent Graduate FPGA Engineers
  19. Spartan-3E Sample Pack
  20. PCI Configuration access and Target State Machine...
  21. microprocessor design: where to go from here?
  22. Progress bar in ISE 8.1
  23. Have you ever considered of mousing ambidextrously?
  24. Does support Partial Reconfiguration FPGA other companies except for Xilinx?
  25. Virtex-4 BRAM control signal inversion
  26. Can one use MGT clock input for global clock in Virtex4
  27. question regarding LUT and MAP
  28. question regarding maximum frequency on virte-e-2000
  29. Historical Fpga Resources
  30. Altera Cyclone II DQ/DQS pins location
  31. Spartan 3 Power Supply Design
  32. CAS signal problem with OPB DDR SDRAM controller in PPC system in EDK
  33. a professional WIRELESS FORUM
  34. Microblaze FSL peripheral problem
  35. Support software for XC3042
  36. Getting started w/ Aurora Core
  37. What will the next FPGA IP-blocks be?
  38. bvci protocol for fpga
  39. HWICAP with the Virtex II Pro. Anybody? Bueller?
  40. where can I find the simulation model of the sram, ISSI61LV25616?
  41. Freeware request
  42. EDK : PPC405 Interrupt question
  43. Instantiating addsub, comparators in Xilinx
  44. Sell high quality HDI PCB (CHINA)
  45. help!! my modelsim occur error on strting
  46. Spartan 3E 500 DCM fine phase shift doesn't work
  47. SerialATA with Virtex-II Pro
  48. CCLK does not start up on boot
  49. replacement of opb_mdm core for ML401 kit: opb_mdm_v2_01_a
  50. Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file
  51. PowerPC Problems in Virtex
  52. SDRAM controller selection
  53. Using the IEEE Std 1532
  54. risc processor in altera up3 kit
  55. Debugging ideas.
  56. Urgent Help Needed!!!!!
  57. Where are FPGA heading?
  58. ISE 8.1 linux 64bit license key
  59. Sell Print Circuit Board --(CHINA)
  60. ADC Interleaving
  61. Purchasing Virtex-4 FPGAs
  62. ANVESHAN TELECOM OPENINGS FOR Embedded/DSP 1-6 yrs exp- mail to [email protected]
  63. CoolRunner 2 CPLD
  64. Any PCAD users here by any chance?
  65. CSV files available for Xilinx FPGA parts pinouts?
  66. Multiple clocks design
  67. Variable problem
  68. Spread Spectrum Cores ??
  69. reading data off a virtex-ii pro board
  70. Using XMD to upload from board
  71. Why Xilinx does not specify clock to output MINIMUM time???
  72. boundary scan example with spartan3
  73. Altera FIR compiler
  74. DSP Builder @ System Generator
  75. Spartan 3 DCM
  76. PacoBlaze update
  77. About Altera FPGA Board
  78. How do I handle this memory related issue?
  79. Coregen in ISE 8.1i webpack not working quite right
  80. debuging power_pc + microblaze
  81. xiilnx spartan 3 starter kit connection to Ethernet LAN
  82. PROBLEMS WITH COOLRUNNER XPLA3
  83. Soldering SMT/BGA
  84. Why does Xilinx hate version control?
  85. Doubt on the xilinx Viretex E user guide
  86. FPGA Design Implementation
  87. What does a "1RW/1R Partial Write RAM Verilog HDL Model." usually. mean?
  88. Xilinx DDR SDRAM Controller
  89. Sell high quality HDI PCB (CHINA)
  90. How to specify a package in Xilinx 8.1i
  91. using EDK with the gcc -g option...
  92. Question about multi write ports RAM in FPGA?
  93. Question about multi write ports RAM in FPGA?
  94. LEON processor core
  95. Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.
  96. Plateform FLASH PROM configuration using a Microblaze.
  97. ModelSim 6.0 v 5.7 Can't read file
  98. synthesis time with XST
  99. (no subject)
  100. AC97 Codec
  101. Z80 Support Cores
  102. EDK8.1: Is adding IP core parameters stiil possible?
  103. Someone need to port LwIP to ll_temac core/wrapper?
  104. Learning new stuff about FPGA
  105. Call for Papers with extended deadline: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)
  106. EDK: DCR bus doesn't work
  107. Problems with Output pins on XUP board
  108. a problem with coolrunner CPLD (XC2C256) GCK0 pin
  109. Nios2 and Shared Bus Resources
  110. FIFO Simulation Oddities!
  111. Virtex-4 DCM CLKFX jitter
  112. New Sydney-X2 FPGA development system
  113. Altera PowerPlay Analyser
  114. a professional bus community and resource
  115. since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)
  116. slice macro replace the bus macro in the virtex-4 how to do that?????
  117. DDR for Spartan 3
  118. Troubles when upgrading Embedded Virtex-4Fx PowerPc
  119. delay in altera cyclone about led
  120. XST issue / Answer record does not help
  121. Inferring RAM from array of records
  122. Re: for all those who believe in ASICs....
  123. Xilinx ISE 7.1.4: Timing Contraints/Fan-Out/Placement
  124. Problem Solving Skills
  125. need doc's for Insight Spartan II demo board
  126. need doc's for Insight Spartan II demo board
  127. Shift Register synthesis??
  128. problem
  129. EDK remote TCP debug
  130. Parallel readback on Spartan IIE
  131. Connect USB device to Spartan 3 FPGA
  132. XST synthesis gripe/sub-optimization
  133. can bus protocol on fpga
  134. V4 LVDS_25 IBIS models
  135. VHDL
  136. 5v Xilinx development board
  137. FPGA imple. of aes
  138. ISE 8.1: simulation modelsm & tbw generated in Verilog instead of VHDL?!
  139. Does xilinx ise 8.1 support linux red hat 4.0??????(with device Spartan-3 400k)
  140. DCM question
  141. Sell high quality HDI PCB (CHINA)
  142. Crosstalk Analysis on a FPGA
  143. how to implement a good register decoding logic
  144. speed control ac motor in FPGA
  145. Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
  146. for all those who believe in ASICs....
  147. Questions about counter in VHDL
  148. recommendation for JTAG Boundary Scan software??
  149. Call for Papers: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)
  150. Xilinx ISE8.1 & MIG1.5 crash
  151. Xilinx LVDS
  152. Atmel using Xilinx FPGAs
  153. Internal pull down on the FPGA.....
  154. Total 35$ Sell 10 piece 2-Layers+Silkscreen+Soldermask PCB (CHINA)
  155. Internal Signals in OPB EMC In XIlinx PLatform studio
  156. Microblaze multiplier Virtex2pro vs. Spartan3e
  157. A few questions about FPGAs
  158. Terminologie/knowledge issu
  159. Retiming a datapath
  160. Hitech Global
  161. Asynchronous FIFO design question
  162. ac97 codec on xupv2p
  163. Power estimates in XC3S1500
  164. what do the following constraints mean?
  165. Simulating a ppc working with external memory
  166. Vccaux regulator
  167. latticexp
  168. Pullup questions on Spartan3
  169. processor bus tristate at two places
  170. Simulation of Xilinx Rocket IO
  171. How to interface ASIC on a PCB and and an FPGA
  172. ISE freezing up with picoblaze code.
  173. How to choose FPGA/CPLD ?
  174. Par error in Spartan-3
  175. Par error in Spartan-3
  176. Which CPU and Screen Rez for ISE 6.3i ?
  177. Question for the EDK ppc users ...
  178. FpgaC Beta-2 release on sourceforge.net today
  179. Hollybush1 - PC104+ Board
  180. The IDE interface
  181. can I port ppclinux to virtex4-fx?
  182. EDK: choices for simple internal control
  183. why use an FPGA when a CPLD will do ??
  184. Xilinx Coregen
  185. bscan_virtex4 device
  186. Virtex-4FX MiniModule Atmel Flash
  187. Simple ADS5273 -> Xilinx Interconnect Model
  188. Device ID of GPIO
  189. Device ID of GPIO
  190. Device ID of GPIO
  191. Using time.h in EDK
  192. Broaddown4 - Ultimate Virtex-4 Development Board
  193. ISE WebPack and Bitstream encryption
  194. Spartan 3 Expansion Board
  195. Assign FPGA pins to submodule
  196. DMA and PCI in SoPC Builder
  197. PPC LUTS registers
  198. I want to use UltraEdit as a text editor for ISE
  199. Help wanted
  200. coregen on webpack 8.1
  201. rocketio in serdes mode
  202. Virtex4 MGTs using Aurora Core
  203. i2c addressing
  204. Xilinx MIG
  205. Pulse Shape in a functional simulation
  206. problem with ISE versions
  207. Virtex-4FX Mini Module TEMAC examples
  208. Microblaze on Spartan3
  209. Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
  210. DDR2 FPGA PWB SIMULATION
  211. floating point MAC, duh!
  212. FPGA communication, I2C and DAC
  213. XUP Vertex II J5 Expansionheader Voltage
  214. PPC Linux SoC on Virtex4 in 4 hours !?
  215. conv_integer
  216. 32 bit select map
  217. Xilinx MIG
  218. How do I make dual-port RAM from single port RAM?
  219. New XC9572 decoupling newbie question :-)
  220. Observed a bug in the Model sim V 6.0a
  221. Why wouldn't this infer a flop with async reset and sync enable
  222. System crashes when configuring altera stratix pci board
  223. PCI configuration for ML310
  224. NGCBUILD .. MDT error on Virtex 4
  225. VirtexII routing data widths
  226. Virtex-4 RAMB16 relative placement
  227. Serious problem with XST
  228. FPGA: Model-SIm XE problem
  229. tricks to make large PLAs fast?
  230. miniuart
  231. Coregen ISE 6.1
  232. ERROR:MapLib:482
  233. VGA specification
  234. Virtex 4 Multiplier RPM Constraints?
  235. about Xilinx Chipscope
  236. FIFO design
  237. XC9500 JTAG Initialize problem
  238. fpga to 5v ttl logic
  239. Low power consumption board with memory
  240. VHDL to create LUT based delay
  241. Loop Optimization
  242. A dev board supporting partial/dynamic reconf.
  243. V4 FIFO16 and SRAM
  244. How about a "File Exchange" for System Generator designs?
  245. Module-based partial reconfiguration in ISE Webpack
  246. FPGA Selection Question
  247. Problem after P&R using Xilinx Viterbi Decoder IP
  248. Call For Papers: Applied Computing, Computer Science and Eng. Conferences, June 26-29, 2006, USA--WORLDCOMP'06
  249. [EDK] XilNet throughput
  250. System Packet Interface?