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  1. xilinx JTAG
  2. 8:1 MUX implementaion in XILINX and ALTERA
  3. xilinx DCM Timing warning
  4. New FPGA Technology Reaches New Heights
  5. Creating macros
  6. www.buswares.com
  7. decoding
  8. asynchronous FIFO design
  9. C-Compiler for free VHDL controller core ?
  10. DDR Termination
  11. Compiler to FPSLIC
  12. Why does Synplify add clock buffers?
  13. FPGA FAQ and the spam problem
  14. Help needed
  15. who know what is the problem
  16. who know what is the problem
  17. Infer dual-clock block RAM for Xilinx
  18. what is architectural diffrence between block ram & distributed ram?
  19. shared BRAM between PPC and FPGA fabric
  20. one question for a error of map
  21. C H S in a Compact flash
  22. Accessing compact flash?????????
  23. Accessing compact flash?????????
  24. Accessing compact flash?????????
  25. rather simple gsr Q
  26. OPB master
  27. gameboy camera to FPGA
  28. Virtex-4 Gigabit Ethernet design
  29. XUPv"P DDR failure log
  30. Altera Talkback
  31. Xst warning, dangling RAMB16B output
  32. Bizarre behaviour by Quartus?
  33. ddr in virtex2
  34. Inferring SRL in Xilinx FPGA
  35. audio codec on the virtex-ii pro board
  36. GOF, Enhanced verilog RTL debug.
  37. Difference in output between testbench and chipscope
  38. RocketIO MGT Clocking Arrangement!
  39. initializing arrays with Verilog and XST
  40. LVDS in Cyclone-II
  41. design flow xilinx ise 7.1+synplify pro8.4
  42. opensource vs commercial
  43. Data Validity and Freshness
  44. seq and comb modules of the FPGA, pls HELP me out !!
  45. burstcount support in Quartus SOPC Component Editor
  46. Final Call for Papers: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)
  47. Delay value for FDDRCPE in Virtex-II Pro FGPA
  48. EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
  49. Compressing DVI stream
  50. I2C bus controller Implementation
  51. XAPP264 OPB slave peripherals using Syustem Generator - help
  52. Xilinx java application freeze
  53. max lvds IO speed on V2Pro
  54. done pin didn't go high
  55. interesting note -- altera C to hardware :)
  56. Dual-edge synthesizable D flip-flop - any pitfalls?
  57. Source-synchronous IO constraints in Synplify
  58. How does the DCM phase shifting circuitry work? Xilinx Spartan 3
  59. Streamlining FIRs in System Generator
  60. Lattice ispLever Starter Download
  61. Altera Stratix II GX LVDS max speed
  62. ISE under 64-bit Linux?
  63. HDL Options @ EDK
  64. System Ace
  65. about the low power design
  66. XUPV2P
  67. xilinx legacy input error
  68. How fast is YOUR ise8.1?
  69. Cheap Spartan 3 PCI express starter kit
  70. xilinx xc2vp30
  71. Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
  72. Sell high quality HDI PCB (CHINA)
  73. Sell high quality HDI PCB (CHINA)
  74. Want HiSpeed USB on your FPGA ?
  75. why the best code are the random codes ?
  76. Xilinx XST incremental synthesis tooo slow
  77. DMA with EDK
  78. embedded design prototyping
  79. Virtex-4 readback via ICAP
  80. w
  81. Spartan3E data sheets
  82. Looking for chebychev equation
  83. Spartan 3E SPI Programming
  84. virtual slot implementation
  85. Problem erasing EEPROM XCF08P
  86. Inferring RAM with FOR loop
  87. Sell high quality HDI PCB (CHINA)
  88. Xilinx Kernel
  89. wireless and bus
  90. Xilinx SelectMAP problem
  91. Modular Design and Incremental Design in ISE
  92. KEEP_HIERARCHY
  93. Atmel microcontroller
  94. Hierarchical FSM?
  95. Concatenate String in Verilog?
  96. Discrete
  97. Virtex II Pro
  98. Testing sample Aurora design on ML321 board
  99. Configuration pins on Spartan-3
  100. ModelSim 6.0 missing Structure
  101. FIFO Vs Shift Register
  102. Doubt about SERDES
  103. ModelSim Designer
  104. <%><%><%><%>HOW TO BE FUNNY!<%><%><%><%>
  105. >@>@>@>@>GET MORE CHICKS............LEARN GUITAR.............
  106. <><><><><><><>The Net's #1 Joke e-Book!<><><><><><><><>
  107. Spartan3E Phase-Shifter
  108. Xilinx Webpack vs Foundation ?
  109. hwicap can be used in the virtex4
  110. JTAG program failed
  111. <%><%><%><%>HOW TO BE FUNNY!<%><%><%><%>
  112. test(null)
  113. >@>@>@>@>GET MORE CHICKS............LEARN GUITAR.............
  114. Amnesty for illegal immigrants will not happen this time.....................
  115. Error : iMPACT 1208 : -'1' Boundary-Scan chain test failed at bit position 1
  116. Will illegal immigrants get deported?.........Of course not.....................
  117. Synplicity cuts structured ASIC tools, 8% of workforce
  118. Illegal Immigration, the Non-Issue of the Week??????????????
  119. Picoblaze, UART: need help!!
  120. design compiler optimization
  121. ISE 8.1, EDK 8.1 installation
  122. no output from BUFGMUX
  123. question about Virtex-II Pro program execution time
  124. BlockRAM
  125. Interface Problem
  126. Xilinx Schematic Entry
  127. GTKWave 1.3.86 for Windows is available
  128. Help needed
  129. USB Interface to Virtex-4
  130. need your comments
  131. USB phy in dev board
  132. problem block ram modelsim
  133. H.O.T. II - Virtual Computer Corp Hardware Object Technology Development System
  134. PCB Bypass Caps
  135. how can one get a netlist consisting of SLICEs?
  136. FpgaC developers wanted :)
  137. how to read this book« Digital integrated circuits.a design perspective(Second Edition)»
  138. FSL to VHDL interface
  139. two professional technology forums
  140. Final Call for Papers: IMECS 2006 (the multiconference of 14 engineering & computer science conferences)
  141. Xilinx ISE DRC: An antenna found
  142. free synthesizer to synthesize VHDL to Actel 1280XL FPGA
  143. free synthesizer to synthesize VHDL to Actel 1280XL FPGA
  144. Stratum4E holdover
  145. problem with IO in EDK 8.1
  146. Storing variables into data ocm memory
  147. Cyclone II EP2C70 dev kits, where are they?
  148. how to immitate clock behavior----Please guide
  149. How to set the Chipscope trigger to the very start of the user appl?
  150. Question about: Logic Levels in Critical Path
  151. Keystroke saving w/ IEEE.Numeric_Std
  152. xst and fpga express
  153. EDK/Xilinx : Insertion of ECC capability into BRAM controller
  154. basic doubts about chipscope pro
  155. combinatorial always blocks + for-loops in XST
  156. Specifying top level generics with XST 7.1
  157. actmap looks like not responding
  158. actmap looks like not responding
  159. Bidirectional signals with Altera Signaltap
  160. OPB monitor error
  161. Please recomend textbook with AES encryption.
  162. Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
  163. WARNING:Xst:1778 - Inout <AddrBus>
  164. ERROR:Xst:827 - bad synchronous description
  165. deglitching a clock
  166. OPB IPIF Master Support
  167. Opb Spi Controller Trouble
  168. Variable Bus Input/Output Fifo
  169. Verilog, PSL or SystemVerilog of OVL?
  170. spartan FPGA with PLCC package
  171. Linux on ml403
  172. Spartan 3e Starter Kit finally available? No, not really.
  173. Sell high quality HDI PCB (CHINA)
  174. Clock multiplication without using the Xilinx DCM's
  175. Altera web site inaccessible
  176. need help,test on Spartan3 starter kit
  177. EDK 8.1 Problem: Adding *.h or *.c files ?
  178. ERROR:NgdBuild:604
  179. chip reverse engineering
  180. BlockROM inference in XST - This is just plain silly
  181. C-based FPGA programming/mixed languages
  182. Nios II - Branch Prediction
  183. Nios II - VHDL Source Code, Licensing
  184. I am a bit stuck with error INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1
  185. Spartan-3E 500 and PCI 33/66 design
  186. Test bench waveform bug
  187. Verilog RTL and Behavioral Testbench
  188. How to write compact DFF chain?
  189. Verilog Task pass value problem?
  190. Share Your Articles on any FPGA Technology with public
  191. Multithreaded NIOS II or other embedded cores
  192. System design methodology
  193. linux on memec fx12 mini-module?
  194. FPGA introduction/FAQ?
  195. How to do profiling on hardware target on Microblaze
  196. Support for Precision2005c
  197. dai
  198. FPGA : HSWAP
  199. Accessing ModelSim Environment variables in Verilog code
  200. TNM propagation: I seem to be having trouble
  201. Data Muxing on Spartan3 using the embedded carry chain
  202. Memory leaks with ISE 8.1
  203. Pacman update
  204. Xilinx hi-speed interconnect/routing question
  205. Timing Diagram software recommendations?
  206. Digital filter design software?
  207. Searching Dallas DS 2432 P or P+
  208. Number of taps for a FIR
  209. Changes on xapp765 for ISE/EDK7.1 and 8.1?
  210. help on RISC controller developed mikej
  211. FPGA : Spartan-3e configuration failure
  212. asynchronization FIFO in HDL co-simulation
  213. Xilinx ISE tutorial revisited using MyHDL
  214. Xilinx ISE tutorial revisited using MyHDL
  215. XST takes unusually long
  216. false paths in Actel flow
  217. Installing ISE 8.1i - don't use a space in the install path
  218. FPGA/ASIC Designer needed at Motorola Mobile Devices in Austin, Tx
  219. Spartan2 and Spartan3 BlockRAMS Can they work thesame?
  220. Difference between Xilinx shift_extract and shreg_extract constraints?
  221. Problem with LwIP and MicroBlaze
  222. this JTAG thing is a joke
  223. Xilinx RAM16_S9.V model syntax problem
  224. Going from CLK1X to CLK2X.. really safe?
  225. Those yellow markers .... (ISE8.1)
  226. regarding synopsys design anlyzer
  227. error from synopsys design compiler
  228. Lattice FPGA
  229. Are Quad-processors advantageous?
  230. Verilog's integer and reg?
  231. JTAG programing specs for XC18V01 PROM
  232. FPGA
  233. need help on asynchronous buffer
  234. ISE usage help
  235. need help with vhdl code in custom IP
  236. Smarter Power supplies arrive
  237. need help on 16 bit risc processor code
  238. How to get eps file from XST RTL viewer for LATEX
  239. BRAM for virtex-4
  240. OpenSPARC released
  241. Virtex-4 RocketIO and G.709 OTU-2
  242. Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
  243. Self-check Testbench Learning
  244. Xilinx Square Root Unit
  245. Ignoring hierachy while flagging false with with Xilinx flow.
  246. Visit www.fpgasps.com and Win FPGA Development Kit worth US$199
  247. Visit www.fpgasps.com and Win FPGA Development Kit worth US$199
  248. Virtex 4 deconfiguring itself ...
  249. Ace file for design with dual ppc405
  250. Simulation tool