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  1. ---Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
  2. How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
  3. PLB transfers: PPC to IP
  4. Need help reattaching top to FPGA
  5. PCI Design
  6. Running Xilinx and Altera Tools on Fedora Core 5
  7. Aurora sample design: Testing/Eye Diagrams
  8. OVERCOAT - FPGA Development Arrays
  9. reverse from jedec to abel
  10. generating IP cores
  11. generating IP cores
  12. Mains pick-up on I/O pins
  13. Power Up delay in FPGA !!!!!
  14. PCI Header types !!!
  15. Personalization of Xilinx ISE
  16. IOB IO Standards in Spartan 3
  17. System Generator cc1 error
  18. hard disk drivers problem
  19. How to add a peripheral IP generated by Coregen to EDK?
  20. Fast Serial I/O on Virtex-5
  21. JTAG in-system programming of PROM devices
  22. PCI related doubts !!!!!!
  23. ngdbuild:604 - storing netlists in other directories than the projectdir
  24. XC9572 Readback
  25. PCI related documents
  26. ISE 8.1 with 7.1
  27. Specifying a non connected port
  28. Low Cost High quality pcb prototype and Assembly manufacturer(CHINA)
  29. fpga uclinux, good starter board ?
  30. COREGEN: DCM
  31. Peripheral connected to multiple OPB buses
  32. DVI connected to Virtex-4
  33. need a date look here
  34. Potential of the CELL Processor for Scientific Computing
  35. tft and uClinux
  36. Xilinx EDK library size issue
  37. initial block processing in XST 8.1, part 2
  38. Xilinx IP wizard help
  39. DCM lock - require clarification
  40. Agility - user experiences? (newbie)
  41. ADV7321 interlaced mode
  42. FPGA : FFT
  43. Altium Livedesign eval boards - can you add a configuration prom?
  44. Synthesizing VHDL delays [noob]
  45. DSP48E, What are the internal implementations used?
  46. Startup in Dynamic Reconfigurable Computing needs a FPGA Designer
  47. Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
  48. using Altium DXP2004 with Virtex4, also soft processors
  49. ISE .ant file
  50. Metastability question (newbie)
  51. ChipScope and the FPGA Editor ILA command
  52. Quartus and Cygwin X-server
  53. problem programming Altera Cyclone device
  54. how to readback a frame
  55. Embedded Programming of Altera EPCS device
  56. XdmHelpers:662
  57. Report for routing resource usage?
  58. Opening for a Director of Hardware Development (ASIC/FPGA)- Network Security Systems- Austin, TX
  59. setting max fanout with xps flow
  60. Stopping Quartus using multipliers?
  61. System Generator Eval version for Malab R2006a
  62. fpga debug
  63. WebPack ISE 8 - how to avoide 'non supported language' warnings?
  64. Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
  65. Config XCF04S using iMPACT
  66. FPGA : Constraint for BRAM placements
  67. FPGA : P&R problem - Help !
  68. Reading from and Writing to J3 Intel StrataFlash NOR FlashPROM on Spartan3E SK
  69. Verilog vs VHDL
  70. I2C on Xilinx V4
  71. .hex or .svf file from Mediatronix picoBlaze IDE
  72. PCI 64/66 fpga eval boards
  73. FPGA delay generator
  74. someone used FIFO along with the OPB-bus in FPGA ?
  75. OPB Timer MicroBlaze
  76. ISE 8.1SP4 PN doesnt start
  77. Xilinx -- please help with Virtex-4 datasheet
  78. ModelSim Designer
  79. i need glasses
  80. Possible output drive strength when using Micron DDR and Stratix II DDR Controller
  81. FPGA PCIe core connectivity w/ a PC
  82. Building a board with Spartan 3 FPGA.
  83. xilinx pricing discrepancy
  84. Independent clock FIFOs
  85. Urgent help programming SPI-flash trough JTAG (Spartan3E)
  86. incremental chip building in ISE
  87. Unknown Processor Version (8)
  88. MicroBlaze and IIC
  89. [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
  90. Low Cost High quality pcb prototype manufacturer(CHINA)
  91. How simple can FPGA design be? (Mission Possible 2006)
  92. Quartus ByteBlaster in Active Serial Programming mode not working
  93. MicroBlaze as SubModule Problem
  94. Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
  95. JTAG chaining of two different Xilinx Spartan 3E boards
  96. Signal 2 clocks long but only one clock possible
  97. initial block processing in XST 8.1
  98. Why do the electronics manufacturers have to spam me?
  99. Why do the electronics manufacturers have to spam me?
  100. ispLEVER Starter 6.0 FPGA Design Software Available
  101. xilinx V4 obufds_25 and 3.3 V
  102. PLB clocking
  103. Re: CPLD (CoolRunner failures)
  104. Xilinx/Synplicity LUT Placement
  105. [Newbie] Suitable FPGA for my project
  106. CPLD (CoolRunner) failures.
  107. Xilinx-ise, invert input?
  108. Use USB ports on ML401
  109. LISP Workshop at ECOOP06
  110. Ethernet & ML401
  111. Memory Interface: Standards
  112. generate a square signal with a 3.8 ns "plate"
  113. EDK OPB DDR2 IP Core, looking for tested example
  114. Error in XPS 7.1 mb_opb_wrapper
  115. Spartan 3e sample: pack power control with M(1)?
  116. Processing DVI signals with an FPGA
  117. V5 and carry lookahead
  118. DCM and Clock
  119. Output gain adjuster of digital filters
  120. Spartan 3 Readback
  121. FPGA Configuration Question
  122. OFFSET constraints with derived clocks - Xilinx FPGA
  123. FPGA and Reconfigurable Programming Glossary
  124. Clocking ZBT RAM via DCM on ML40x board
  125. Where can i get "Quartus II Device Information for UNIX & Linux CD"
  126. Update: Simple ADS5273 -> Xilinx Interconnect Model
  127. V4 system synchronous input setup/hold and clock-to-out time calculations?
  128. Verilog Draggable Window Library
  129. Looking for DDC/DUC customizable cores
  130. Cyclone II PCI & Pin Swapping
  131. DCM
  132. Hold Time Violations in Virtex4
  133. CoolRunner Pins during Programming
  134. ANNC: ISE/WebPACK 8.1i tutorial available
  135. SystemACE bootloader for PowerPC on Virtex4 FX
  136. disappointing 550Mhz performance of V5 DSP slices
  137. EdaXML
  138. ADC implementation on FPGA ?
  139. hy I need a code example for spartan 3 series in Xilinx regarding the implementation of a PID alghoritm
  140. SPI master
  141. XilKernel and Budgeting
  142. Shared Memory
  143. Virtex4 FX12 dynamic clock divider
  144. sending multiple char on RS232
  145. I can't connect to my Spartan 3 !!! ( Digilent starter kit )
  146. WARNING:iMPACT:923 - Can not find cable, check cable setup !
  147. Xilinx or Altera...
  148. requirements to select FPGA using LVDS
  149. Synplify Pro warning - cudnt understand
  150. Actel Fusion FPGAs
  151. USB2 camera to Xilinx ML40x boards
  152. Microblaze dcm_module problems
  153. Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
  154. New Virtex4 Project, CoreGen
  155. Xilinx XC4000 series
  156. Need help with old Xilinx project
  157. uClinux on MicroBlaze: Can't ping now
  158. Virtex 5 announced
  159. IEEE-1394 (aka FireWire) Core
  160. pull-ups and jtag questions
  161. Make a signal free for glitches?
  162. Re: Assigning MGT's in sample Aurora Design
  163. safety critical applications with FPGAs/CPLDs
  164. How to decide Setup/Hold time values ?
  165. How to decide Setup/Hold time values ?
  166. getting good deals on small qty?
  167. Files.ucf QAM Demodulators for Xtreme DSP Development KIT
  168. Floating point reality check
  169. Amontec Komodo board ?
  170. Raggedstone IO bracket ?
  171. Spartan 3E
  172. ADD WINGS TO YOUR RESUME !!!!
  173. Picture frame
  174. filter design
  175. Trouble understanding Synplicity timing report
  176. altera cyclone memory example
  177. USD$35 manufacture 2layers+2silk+2mask pcb prototype(CHINA)
  178. ISE 7.1 synthesis problems
  179. ISE 7.1 segmentation faults
  180. Synchronous Scrambler
  181. How to decide Fanout limit?
  182. difference of variable and signal
  183. How to check IOB register packing?
  184. clock multiplier in spartan 2
  185. JTAG tutorial
  186. Multiple Write Port Register Files
  187. can increase simulation run time while running modelsim?
  188. computer bus technology discuss community
  189. Synplify - Not satisfactory results with re-timing option
  190. ISE 8.1 error, help. Or where is the path?
  191. ISE 8.1 error, help
  192. Power for Spartan 3
  193. MicroBlaze GPIO 1-bit [resistor], funny story :)
  194. sqrt(a^2 + b^2) in synthesizable VHDL?
  195. XCFxxP Plaform Flash Device Questions
  196. How can I get internal signal in modelsim.(Xlinx ISE),timing-simulation
  197. How can I deal with the output signal in testbech?
  198. reverse engineering ?
  199. Xilinx warning for DCM
  200. CoolRunner XPLA3 thriving for many years to come
  201. Altera Equiv.
  202. [Newbie] 64-point complex FFT with 32 bit floating-point representation
  203. CoolRunner XPLA3 getting axed?
  204. Quartus II 6.0 available
  205. EDIF simulator???
  206. jhdlbits: source files
  207. Unable to debug MicroBlaze in SDK (Eclipse) and the Software debugger
  208. Routing problem in PAR.
  209. Interrupt signal sampling (Level or edge?)
  210. Altera Max Plus II to Quartus migration tool
  211. High quality pcb prototype and Assembly manufacturer(CHINA)
  212. simulation works fine but the actual chip doesnt work
  213. constraints for DDR bus with 133MHz write and 66Mhz read clocks
  214. Superscalar Out-of-Order Processor on an FPGA
  215. ml-403 and USB
  216. Max operating freq in a breadboard
  217. TME Free Verilog/VHDL framework generation tool
  218. Xilinx ISE 8.1 Makefile
  219. Using vector condition at transition in StateCAD
  220. help me to about clock in fpga
  221. Chipscope and FPGA
  222. Crossing clock domains
  223. UK source for Digilent S3 board?
  224. Putting the Ring into Ring oscillators
  225. PCI Express and DMA
  226. Programming the JTAG flash in circuit
  227. Installing BFM toolkit
  228. Strange power up issue on Virtex4
  229. PCI Core compatibility
  230. booting problem ML300 :eth0: Could not read PHY control register; err
  231. Can an FPGA be operated reliably in a car wheel?
  232. Funky experiment on a Spartan II FPGA
  233. The differences between behaviors of 'std_logic_vector' and 'unsigned'
  234. EDIFParser in JHDL / EDIF simulator?
  235. A constant value of 0 in block
  236. FPGA implementation of an OFDM-based modem
  237. flashing a led
  238. Spartan 3e starter kit & Multimedia
  239. FPGA-based hardware accelerator for PC
  240. Anyone use Xilinx ppc405 profiling tools?
  241. Xilinx document timing diagrams?
  242. Xilinx SelectMAP Question
  243. Xilinx-XUPV2P- AC97 Audio BSP
  244. OPB clocking question
  245. RFID chip has battary in it or not
  246. LVDS inputs on Cyclone II
  247. 87C52 & 87C51 core
  248. New To FPGA, Program question
  249. how to set a I/O as 3-state in xilinx FPGA?
  250. async. load line on shift register