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  1. Missing ISE HTML online help (pdf sucks!)
  2. lwIP on Xilinx Virtex 2 Pro
  3. rocketIO simulation
  4. Nu Horizon Xilinx 1500 fpga board
  5. property of lockett
  6. Help on simulating ddr controler generated by MIG!!
  7. Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
  8. Pc and xcv200e doesn't talk,not exactly the right cable maybe..
  9. How to evaluate the space efficiency of a historic design.
  10. Altium Designer LiveDesign Evaluation Kits (once again)
  11. help downloading picoblaze from xilinx
  12. RS232 transmitter core--Xilinx xapp223(Chapman's macro)
  13. Generic synthesis target in Synplify Pro
  14. Xilinx BUFGMUX Setup Time requirement clarification needed
  15. Problem to extend Xilinx GSRD Design
  16. Stopping the clock for power management
  17. EDK: Using DCR bus on ML310-based project
  18. NCO Clock driven Designs in FPGA
  19. ANNC: x8 PCI Express w/ FPGA Webcast
  20. xilinx ml423 boards available ?
  21. How to comm with Altera JTAG UART (from custom host software)?
  22. DDR2 at 125MHz or lower with Cyclone2
  23. Virtex5 Availability
  24. Synplify prepending Z's to top level signal names in Verilog
  25. Spartan 3E, Output File
  26. Reverse engineering has the protection of law in the U.S.
  27. Spartan3e starter kit vga mod
  28. PLB IPIF Master Read Failure
  29. X-Ray Inspection System
  30. Preserve patent materials through a notary
  31. Montavista linux Xilinx Virtex4 ML403
  32. dcm clkin_divide_by_2
  33. Once synthesized RAMs are vanishing in WebPACK 8.1i03
  34. XilFatFS and CF...
  35. Help in the platform studio(EDK)
  36. need help plz.
  37. Synplify & Fedora core 5
  38. Number of bonded IOB's
  39. XC3SE available
  40. Webpack ISE 8 and Vertex4 XC4VLX60
  41. Xilinx 7.1 ISE : Problem while doing post place and route simulation
  42. Accelerated Bioinformatics Data Processing Solutions
  43. ISE WebPack 8.2
  44. Xilinx ML461 memory board, whats the real story?
  45. Raggedstone1 Brackets
  46. PicoBlaze and DDR Ram
  47. Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
  48. Synthesis problem with ranged integer
  49. VHDL model for Micron SDRAM simulation ?
  50. problem in simulating FFT core on ISE 7.1
  51. Test:PRBS
  52. multisource on signal in XPS
  53. newbie wants to do VHDL on an FPGA
  54. Spartan3E Starter kit on Linux?
  55. A very cool ftp
  56. no ram core simulation with free Ise ?
  57. Xilinx cable drivers for Linux 2.6.16?
  58. Spartan3 or 3E pins to GND
  59. Achieving timing in Xilinx EDK designs
  60. Optimization of Multiplication in FPGA
  61. is picoblaze worth in my project?
  62. stimulus for FPGA
  63. Xilinx RocketIO receiver reset problem
  64. Aurora 4 byte interface
  65. Aurora 4 byte interface
  66. Spartan 3E Starter Kit - diff b/t rev. C and D?
  67. RS232 to access TX registers of Aurora
  68. Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
  69. Amirix AP120, U-Boot and uartlite
  70. newbie:my ISE doesn't include old xcs30 spartan how........
  71. Remote access to Altera FPGA via jtagd in Linux
  72. Newbie in Chipscope-changes need to route bidirectional data port
  73. Xilinx Library Conversion
  74. Linking/mapping code sections with Xilinx EDK
  75. XST crashes & websupport denies access
  76. Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
  77. Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
  78. Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
  79. SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
  80. using Celoxica's RC10 with microblaze's EDK kit
  81. Xilinx XC4VSX25 development board?
  82. Spartan-3 starter kit strange problem
  83. cache aware programming
  84. Actel FUSIN chips are real !
  85. PCI Express - Root Complex Emulation
  86. Stratix column and row pins
  87. xst can, but vcomp can't
  88. comp.arch.fpga : Selection of Device
  89. Synplicity PREMIER
  90. keys to the Kingdom
  91. For Broaddown2 Owners
  92. Instrumentation Technologies
  93. Need help reg Power Estimation using PowerPlay
  94. Xilinx ISE 8.1i Trouble
  95. Google FPGA Designer beta release
  96. FSM State Minimization on FPGAs
  97. Quartus 6.0 Fitter Critical Warning
  98. JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
  99. Microblaze, -mxl-gp-opt and small data areas
  100. Programmable clock ics8442
  101. Processor Design
  102. Virtex-4FX embeded MAC and Rocket-IO data corruption??
  103. Xilinx bitgen vs output file name
  104. Aurora core example simulation
  105. using Impulse-C free edition for VHDL only FPGA designs.
  106. xst:What happened here?
  107. ABEL to VHDL translate
  108. Utility to generate pin assignments (UCF, QSF) from the Protel netlist
  109. --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
  110. Newbie to FPGA
  111. pad issue
  112. Temperature sensing diode on Vertex 4
  113. High speed differential to single ended
  114. Floppy to FPGA?
  115. Doubts on IBUFGDP
  116. Hold margin for asynchronous Interface
  117. bga routing
  118. library for lmb
  119. Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
  120. anybody doing self-timed/asynchronous on post-jbits xilinx parts?
  121. How process statement works in vhdl
  122. Virtex2-Pro local clocking...
  123. Anyone get a Pictiva OLED to work?
  124. Bug in Altera Quartus
  125. Virtex-4 with Rocket IO capability??
  126. ARM cores in FPGA ?
  127. private army of jun g. lockett
  128. XPLA3 bidirectional bus
  129. open inputs and Unisim libraries
  130. LVTTL or LVCMOS for PCI Signaling?
  131. Xilinx XST Error
  132. boot mode pins on Spartan3
  133. ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
  134. ARM9 DDR interface
  135. null waveform element and webpack
  136. Quartus 6.0 and VCS
  137. Does anyone have documentation for an insight DS-V2LC board
  138. S3E Starter Kit webcast
  139. ANNC: VHDL Coding for FPGA Webcast
  140. IDELAY clock spec. in Xilinx V4
  141. Virtex-4 FX12: Mini module board from avnet
  142. FSM state minimization with ISE?
  143. FPGA PCB Prototype high quality and quick turn manufacturer!!
  144. Can i use "burstcount" in my userlogic while using Altera SOPC builder 5.1?
  145. Looking for patent attorney specialized in programmable logic
  146. Virtex4 DCM in DRP mode
  147. How to get lowest price for a ModelSim license?
  148. RocketIO AC coupling
  149. xc3sprog -- any updates?
  150. How do I use the DDS core in a verilog flow?
  151. Xilinx timing viloations
  152. from VHDL to FPGA
  153. Xilinx ISE S/W Install kernel version "mismatch"
  154. initialization sequence and auto refresh for sdr-sdram
  155. edk 8.1
  156. Requesting for an Actel Library
  157. xilinx cable 3 doesn't talk with pc,but test ok
  158. Current from FPGA pins to ADC
  159. PCI Express - Root Complex ?
  160. Linux 2.6 for PPC on Xilinx XUP-V2PRO board!
  161. The 3rd International Electronics Design Contest for Students
  162. Good free or paid merge software that edits two similar files?
  163. Jun G. Lockett assasination
  164. stable, tested 6502 core
  165. Space invaders on Spartan3e starter board
  166. Block Ram vs Distributed Ram
  167. Rumor Control:: Will Quartus phase out supporting AHDL?
  168. Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
  169. Can ILMB and DLMB of Microblaze be 24kByte?
  170. Call for Participation: WORLDCOMP'06 (Computer Science & Computer Engineering), June 26-29, 2006, Las Vegas, USA
  171. Incrmental Compilation in Quartus 5.1
  172. Xilinx SystemACE : Flash Memory
  173. Anyone with Xilinx SP305-board ?
  174. Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
  175. LVTTL, LVCMOS or 3.3V-PCI?
  176. ICAP Virtex4 32 bits
  177. SGMII with Virtex 4 embedded MAC
  178. Problems with ISE logic optimization
  179. Noise-like Vibration in Measurement Result
  180. IOBDELAY's delay value
  181. API on Virtex 4 FPGA or the email of Delon Levi wanted
  182. ise8.1 picking local instead of global clk routing?
  183. EDK: TCL scripts in pcores directories
  184. Propagation delay sensitivity to temperature, voltage, and manufacturing
  185. Xlinix ML403 evaluation board
  186. GPIO problem
  187. ppc instruction count
  188. Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
  189. Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
  190. ISE8.1 on OpenSUSE 64bit
  191. Efficient implementation of Address Decoding logic
  192. FlipChip BGA Conformal Coating
  193. Jtag Programmer
  194. ISE Timing Analysis Misreporting? Bug?
  195. Xilinx Floorplanner basic question
  196. ProjectMgmt WARNING from ISE 8.1i XST
  197. Webpack larger than CDs
  198. The simulation of Xilinx DDC(Digital Down Convert) IP Core can't gain the result
  199. Jumps in Reading out
  200. ..Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
  201. MIL Qualified RTOS for PowerPc 405
  202. Help on DDR SDRAM contoller generated by MIG1.5
  203. How to use usb on Alter EPXA4??
  204. Multi place and route
  205. Documentation miss? (sp3/xilinx)
  206. partial reconfiguration protocol on Spartan II and self reconfiguration
  207. FPGA board for USB experiments?
  208. VHDL code For Floating point adder and Multiplier
  209. Difference Logic Cells <=> Slices
  210. Xilinx ISE 7.1i Tutorial: Test Bench road block
  211. Adding a USB interface to Linksys WRT54G wifi router
  212. Problem with Xilinx ISE 7.1i core generator
  213. WebPack on Linux
  214. Changing the random seed in Xilinx tools
  215. Free Tools
  216. Simulating post par simulation model
  217. Delay or latency
  218. XIlinx 7.1i ISE problem with Spartan 3e design
  219. Building custom ASIC solutions
  220. Using version control for Xilinx 8.1i ISE projects and source files
  221. rise/fall clock edge constraint
  222. Ethernet Snooping in the FPGA
  223. ModelSim: Different SimPrim libraries needed for different Xilinx families?
  224. Driving two DCMs with BUFG?
  225. Using ChipScope with EDK flow?
  226. timings
  227. Xilinx constraining : differential clocks and other details
  228. is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for
  229. Xilinx MapLib:661 errors
  230. DDR SDRAM controller
  231. Problem with Mig1.5 when used to generate ddr sdram controller
  232. RocketIO signal polarity swap
  233. Virtex4 FX12 - maximum frequency for Picoblaze
  234. clockless arbiters on fpgas?
  235. SystemVeriling Synthesis for Xilinx FPGAs
  236. controlling synthesis and implemention with tcl/tk scripts
  237. How many of the old reference sites are still around?
  238. Math Solving, and Statistics Programs
  239. EDA, PCB, Mentor Graphics programs 2006 - , programs,
  240. Tornado, VxWorks, Wind River, ARM, ArmCAD, National Instruments ( N.I. ) programs 2005 -, CDs
  241. Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
  242. Using part of CPLD to Invert Own Clock
  243. Academic scholarships and training on how to program FPGAs
  244. Virtex-4FX12MM: Any hardware MAC address accessable?
  245. combining state machines.
  246. Configuring Spartan 3
  247. Price history?
  248. RocketIO signal polarity swap
  249. Problems simulation plb_gemac core for Virtex-II Pro
  250. Cardbus Power On Reset !!!!!!!!