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  1. generating sine-like waveforms
  2. USB application on ML40X boards
  3. MPD file option HDL
  4. Virtex-4 RocketIO
  5. ISE8.2 + .ngo file + Leonardo
  6. Chipscope
  7. Xilinx: Initializing BRAM content in the ngc
  8. Minimum frequency at which ddr can operate
  9. How do I pass on an integer to a task and compare with an integer in the task?
  10. Generate statements for I/O list
  11. Programmable pulse generator
  12. Implementing Haar Decomposition on 256 sample input using only sysgen blocks
  13. FPGA LABVIEW programming
  14. XPS 7.1 to 8.1 Warnings
  15. Where are Huffman encoding applications?
  16. Virtex4 ML455 do you know this board?... help me!
  17. FPGA : BUG in ISE- View RTL Schematics ?
  18. Usage of DDR IOBs
  19. Quick way to change Xilinx BRAM init values
  20. Lattice Blogs
  21. S3E USB2.0 port
  22. DDR2 SRAM Stratix II questions
  23. MIG 1.6 DDR2 testing problems (FIFO16 related?)
  24. Information required on FPGAs and ARM evaluation boards
  25. Ethernet wrapper IP core with ML403
  26. 100m JTAG cable
  27. Low Cost FPGA Charge Pump Power supply
  28. Core Generator
  29. Problems compiling with ISE Webpack 8.2.01i
  30. Problem with assigning package pins using PACE
  31. Accessing one SDRAM from two MicroBlazes
  32. How do I create a clock with random starting phase?
  33. In a function, how to I do bit-extension on temp variables:
  34. eeNewsFeed.com BETA testers invited!
  35. Interfacing Spartan3 FPGA to 5V PCI
  36. Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
  37. large data access to SDRAM at fixed frequency
  38. "This design element is inferred rather than instantiated" (newbie)
  39. Verilog case statements
  40. 4VSX35 LOC placements?
  41. Spartan3 5V PCI
  42. Does MAC FIR filter need special care?
  43. OT (2nd try): do you get paid for your travel time?
  44. Wanted: CPU config register code generator
  45. Rocket IO as a high speed sampler
  46. Guided MAP/PAR in ISE
  47. Flashes of Light on the Faith
  48. IOBDELAY and DCM
  49. EDK : *.bit and *.elf Files
  50. Hold violation in Virtex 4
  51. Hold violation in Virtex 4
  52. Hold violation in Virtex 4
  53. How to phase align a 10MHz clock using V4LX60 DCM
  54. Spartan 3 clock to output tristate timing
  55. Designing a matrix multpier block using existing xilinx toolbox
  56. Designing a matrix multpier block using existing xilinx toolbox
  57. Designing a matrix multpier block using existing xilinx toolbox
  58. uClinux on Virtex-4 Mini-Module
  59. Issues w/ 8 lane Aurora sample design
  60. Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
  61. FFT module with Virtex-4 xc4vlx15
  62. Virtex4 Rocket I/O. Power filtering.
  63. 2Khz clock signal from 50Hz main frequency with ADPLL
  64. Xilkernel: Using the shared memory API
  65. Calculate CRC in Virtex-Spartan II bitstream
  66. EDK + Assembly Output Files + External Memory Usage
  67. Connecting two buses in Xilinx ISE
  68. impact.log files
  69. Correlator block
  70. Soft processor performance
  71. EDK Using External Ports to toggle FPGA pins
  72. Xilinx Corgen & Synplicity... Anyone? Help?
  73. chipscope opb monitor
  74. ROM implementation
  75. ByteBlasterMV?
  76. Microblaze: how to determine remainder after integer division
  77. ANN: MicroBlaze simulator available
  78. <EDK> PORT .... not found in MPD
  79. Delta sigma Modulator Interface
  80. MGT RXPOLARITY setting
  81. Trouble meeting EMAC RGMII timing in V4FX
  82. KASUMI source code in VHDL
  83. version control of ISE+EDK projects with CVS and/or SVN
  84. Why 8 clock trees in Xilinx Spartan-3 device?
  85. How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
  86. fpgadbg - a free & open source tool for FPGA debugging
  87. Using BUS'es in ISE WebPACK 3.3WP8.1 ???
  88. HW Debug tools
  89. XMatchPRO algorithm on FPGA
  90. IIR FPGA 'crosspost'
  91. PLL clock in in Stratix
  92. Spartan III development: which tools, what kind of PC?
  93. Dparts en vacances et distances de scurit
  94. Linux on an XUP board - cant access user IP!
  95. Using DCM-Virtex-II Pro
  96. Creating EDIF from Verilog, then using VHDL wrapper
  97. system design
  98. clock hold time problems reported in quartus II
  99. tutorial searching
  100. Hardware book like "Code Complete"?
  101. High-speed ADC+ Rocket I/O capability FPGA board
  102. ISE 8.2i and EDK8.1i
  103. MIG DDR2 controller does not work (reset problems?)
  104. ANN: Tyd-IP Code Generator adds NCO design capability
  105. Last Chance for Tarfessock1 Features
  106. Virtex-5: SoftCore processors at 200MHz !
  107. [ANN] RHDL-0.5.0 released
  108. Combining Schematic and VHDL code in Webpack 8.1 ??
  109. Inferring a Xilinx FIFO
  110. Yet another MicroBlaze clone !!
  111. xess board problem (error downloading into ram)
  112. Specify Clock Correction Sequence for Virtex-II ProX MGT (RocketI/O X)
  113. Sorting algorithm for FPGA availlable?
  114. VHDL Data Buffer on Spartan-3E
  115. PCIe: use 8*x1 PHY devices to form x8
  116. Virtex-4 PowerPC and Trace32 ICD - start up help wanted
  117. corrupted data when accessing dual port bram in Cyclone II
  118. Synthesis Problems with Quartus II Version 6.x
  119. Virtex 4 ACE Compact Flash configuration problem
  120. ISE 8.2 - time to crash 20 minutes
  121. Which PCI core for Cyclone II board?
  122. NAND flash hangs
  123. Partial shift register extraction in ISE
  124. Burnig flash image with Xilinx EDK flashwriter tool
  125. JED file translator
  126. GeneXproTools 4.0 - GEP modeling tools for Math and Boolean problems
  127. noob question: reset problem
  128. Call for Sessions Proposals: The International MultiConference of Engineers and Computer Scientists 2007
  129. Opencore ddr_controller
  130. Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
  131. Virtex 4, LVDS I/O: Sanity check please
  132. EDK PowerPC ISS : download errors?
  133. OpenFire - public domain MicroBlaze clone in verilog
  134. FPGA consultants
  135. 2048 input or gate ?
  136. Xilinx System ACE Player available
  137. An idea for a product (FPGA/ASIC based)
  138. Data Logging / FPGA Dev board
  139. Exciting Project!
  140. Virtex4 Mini-Module Phy interrupt
  141. International Journal of High Performance Systems Architecture (IJHPSA)
  142. Post Place and Route simulation for Microblaze....
  143. Using Samsung DDR2 memory with Xilinx Memory Interface Generator (MIG)
  144. Need for reset in FPGAs
  145. design partition across multiple FPGAs
  146. OPB or FSL?
  147. EDK adding custom vhdl with multiple arch/entity
  148. PLB slaves
  149. Separate enable on address for ram blocks
  150. Cyclone II Power Measurement on DE2 Board
  151. issue on on using Xilinx PROMS in conjugation with System ACE;
  152. EDK - Debugging software applications located in ISOCM
  153. ADC08D1500 + Virtex-4
  154. Universal Scan with Xilinx's ML403
  155. Routing Information of Xilinx's Virtex-II FPGA
  156. Raggedstone1 Ethernet Modules Available
  157. Spartan 3E starter kit DDR SDRAM code
  158. Micro-pump is cool idea for future computer chips
  159. about high quality pcb prototype manufacture(Low Price)
  160. Micorblaze post place and route simulation...
  161. reprogram xcf08 serial prom without jtag
  162. Help with RBT file
  163. micron Flash controller VHDL disappeared ??
  164. Can't get my Verilog Peripheral to import into XPS! Any tricks?
  165. Binary Counter Core
  166. Diffenrential I/Os in Virtex-4
  167. Low cost SMD Oven for making SMD samples and Prototypes
  168. how to implement multi-port memory
  169. Assigning unused pins in Quartus II
  170. Virtex-4 Vicm for LVDS with Vcco = 3.3V.
  171. Xilinx Virtex-4 APU Controller Questions
  172. DLL in spartan2e
  173. DIFFICULT MULTICYCLE PATH WITH QUARTUS II
  174. wrapper file error : ports not on the entity
  175. Development Boards -Your chance to suggest features
  176. sopc -apex20ke1500xxxx
  177. Programming the Spartan-3E Starter Kit using Linux?
  178. Implementing USB slow protocol into xilink XC95xxx..
  179. High-speed DAC/ADC with FPGA
  180. P160 Communications module 3 with V2PRO--> EDK 7.1 errors
  181. PROM files: build .bin for daisy chain on the fly
  182. Any *really old* Viewlogic / Xilinx users around here? :)
  183. LUT4 INIT value to implement 2:1 MUX ?
  184. The FFs with synchronous reset perform worse?
  185. Is while loop synthesizable if the number of iterations is known
  186. (no subject)
  187. Weird JTAG lockup issue, where is the BUG?
  188. SP305- PROM configuration
  189. Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
  190. PPC XMK bootloader for ELF files
  191. Xilinx Xcell Journal received damaged
  192. Timing Error in edk 7.1i
  193. Warning issue!!!
  194. FATAL ERROR IN EDK 7.1i
  195. The difference betweeen SLICEM and SLICEL
  196. Virtex4 Mini-Module GBL Phy
  197. PCI IOs, tiofoi, source sampling bypass
  198. recognizing multiple fpga's
  199. Obtain old ver ISE Foundation?
  200. detecting gnd
  201. Can a BUFGMUX drive a global clock in the Spartan-3?
  202. Fastest platform to run ISE?
  203. debouncing a switch (in hardware)
  204. XPS-Microblaze-Xilkernel
  205. FPGA interpolated FIR implementation
  206. Simulation problem for the DDR controller
  207. Xilinx Virtex FPGA designers
  208. DDR Controller problems
  209. How much time does it need to sort 1 million random 64-bit/32-bit integers?
  210. Incorporating CoreGen files in EDK 8.1 peripheral
  211. PLB master without xilinx ipif
  212. xilinx impact : usb failure
  213. High Speed Serial MGTs using Aurora IP
  214. EDK question - debugging PPC405 and MB..
  215. "Large" memory array in VHDL
  216. Can I use all 18bits of a BlockRAM?
  217. mig_ddr_controller
  218. using cores exported from Xilinx plan Ahead with verilg design
  219. Weird timing failure
  220. Xilinx ML403 hard mac (xapp443)
  221. single pad to pad timing in ISE
  222. ADPLL (50Hz to 2kHz)
  223. ASCI to FPGA - require details
  224. 欢迎光临我的单片机博客,资料多多,文 *多多
  225. Altium Live Desing Eval and Linux
  226. UCF File : LOC signal syntax
  227. PPC and Chipscope?
  228. help me please
  229. Inferring multiple-DSP48 pipelined multiplier in VHDL
  230. Inferring multiple-DSP48 pipelined multiplier in VHDL
  231. can't read device ID xcv200....what about the PROGRAM pin
  232. Properties of some pins of Vertex4
  233. Chaos in FF metastability
  234. design in vsprom
  235. LwIP
  236. next EDK service pack release date?
  237. Timing constraints on ISERDES
  238. Synthesis changes after ISE upgrade
  239. Quick Turn PCB Manufacturing - Viafine PCB Manufacturer
  240. how to use the xilinx 18v04 config fpga?
  241. How to trigger write signal and read sigal
  242. component instantiation ISE7.1
  243. stable reset in fpga
  244. Xilinx System Generator Part List Problem
  245. register state when power on
  246. Cyclone-II Configuration via a PCI bus
  247. How to control the uart
  248. minimal connections so that a xcv200e talks with pc
  249. Problem with SLL: "sll can not have such operands in this context" and bit-testing
  250. Pointers for sending data using ethernet connection from V2Pro