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  1. Aurora implementation
  2. Xilinx Spartan-3A
  3. FPGA support for DDR3 and GDDR3
  4. fx12 v fx20 static power?
  5. Virtex-4FX DCM autoshutdown failure, any suggestions
  6. Xilinx - one secret less, or how to use the PMV primitive
  7. behavioral vs post-P&R simulation mismatch
  8. MGT Power supply
  9. power measurement on the board...
  10. FF1152 Development board....
  11. Location of Virtex4 ASCII pinout tables
  12. September training?
  13. Undergrad project-8051 specifications??
  14. Do I need to adjust sdram clk shift when i lower my system clock?
  15. Sun open SPARC micro architecture document
  16. How to load the data off the FPGA to the PC?
  17. Actel Fusion?
  18. Semi-OT: Free (USA) tube of Philips CPLDs
  19. Question on Virtex-4 CLB
  20. FREE Commercial-Grade HDL integration tool Topweaver3.1 released
  21. EDK 6.3 project file growth
  22. synchronisation on rising and falling edges
  23. Spartan-4 ?
  24. Call for Papers: IAENG International Conference on Bioinformatics ICB 2007
  25. FFT IP CORE: XK_INDEX???
  26. FFT : XK_INDEX
  27. FSL read/write problems
  28. Spartan 3 and 5V input
  29. RLC, extraction, and file formats
  30. ask for help about routing/unrouting problems in jbits2.8,thanks
  31. Post-route simulation
  32. placing addiional caps across existing caps to reduce noise
  33. Question about library update in Modelsim
  34. Quartus software and dual-purpose pins
  35. is ISE coded in Java?
  36. Problem with netlister in System Generator
  37. adiabatic and reversible computing with FPGAs?
  38. What is the truth about the Virtex5 ?
  39. Call for Papers: IAENG International Conference on Artificial Intelligence and Applications (ICAIA 2007)
  40. How to change the font size in text editor of modelsim
  41. How to change the font size in text editor of modelsim
  42. FPGA -> SATA?
  43. I2C on Xilinx Virtex-4/ML403
  44. Virtex 4 TEMAC and MII questions
  45. Installing Quartus 6 "web edition full"
  46. UltraController II + SystemAce
  47. Error message in ISE7.1
  48. Xilinx IPIF DMA done interrupt ?
  49. Linear priority encoder in Xilinx Virtex4
  50. Call for Session Proposals: the World Congress on Engineering WCE 2007
  51. Arbiter design problem?
  52. Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
  53. no luck instantiating system.xmp (EDK project file) within ISE
  54. RocketIO over cable
  55. Why isn't there a thermal diode on large FPGAs?
  56. QuickLogic
  57. DDR controller on Spartan-3e 500
  58. Xilinx BRAMs question - help needed ..
  59. Modelsim XE problem with Xilinx ISE 8.1i and 8.2i
  60. ISERDES strange simulation behaviour
  61. high level languages for synthesis
  62. Why No Process Shrink On Prior FPGA Devices ?
  63. ANN: MicroBlaze platform simulator XSIM ver 1.1 released
  64. Block RAM vs Flip Flop
  65. Checking syntax
  66. Style of coding complex logic (particularly state machines)
  67. Global signal conservation
  68. esoteric hardware?
  69. USB PHYs and drivers that folks have used
  70. Xilinx Virtex-4FC PPC
  71. DQPs
  72. Timing
  73. Xilinx Floorplanner
  74. virtex4fx board and ethernet
  75. Here you can read books free and buy all tickets
  76. Modelsim
  77. Microblaze : xil_malloc malloc
  78. Open source Xilinx JTAG Programmer released on sourceforge.net
  79. DCM vs. PLL
  80. uclinux on spartan-3e starter kit
  81. Tip: How To Determine Bandwidth Requirements For Supply Chain Management Systems
  82. New release of HDLmaker
  83. Running DDR below the min frequency
  84. ISE 8.2i and EDK 8.1i
  85. Xilinx Virtual Platform
  86. Xilinx FPGA editor error ISE8.2
  87. PCIe latency
  88. Intermediate and Senior Analog Engineers Needed - Ottawa JOBS
  89. Microblaze - Writing to instruction store
  90. Using multi-cycle contraint and simulate it correctly
  91. Detect failure in Berlekamp algorithm
  92. OFFSET with DCM NET or derived NET?
  93. ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
  94. Davies-meyer in VHDL
  95. ALTERA Automotive Graphics Controller Reference Design--drivers
  96. Please participate in a non-profit academic research
  97. Call for Papers: World Congress on Engineering WCE 2007
  98. ISE 8.1: Process "Map" failed
  99. Xilinx .002ns timing error
  100. hex format 16 bit?
  101. Configuring an Altera Serial Prom/Flash using a 8051 CPU
  102. Xilinx EDK 8.2 released
  103. OpenRISC + DDR
  104. Need some assistance with ISE OFFSET constraint.
  105. Newbie frustration
  106. Modelsim SE Simulation
  107. The warning of VCC and GND is normal in MAP file?
  108. CPU design
  109. ISE/EDK "target pattern contains no `%'"
  110. Xilinx ML501 availability
  111. Warningmessage in ISE
  112. Applications Of 10 Gigabit Ethernet Switching For Today's Enterprise Computing Environment
  113. Speed vs Area Optimisation
  114. Anyone use XC3Sprog?
  115. xc2vp30-6ff1152
  116. Xilinx ise ml402 bram interface
  117. memec-avnet reference designs available
  118. Problem with "don't care"
  119. Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
  120. tcp/ip
  121. Hello Guys, Please let me know if you need any Cisco
  122. Why is Spartan-3 more expensive than Cyclone?
  123. EDK vs. ISE for image processing
  124. Using an FPGA as USB HOST without PHY
  125. DCM and Maximum Frequency implied by XST
  126. FFT on an FPGA
  127. Using XMD for memory dumps (speed)
  128. Reinstalled Quartus + Nios II => cygwin1.dll hell :-(
  129. Call for Session Proposals: World Congress on Engineering 2007
  130. Problems about the synthesis(XST)
  131. xilinx or altera?
  132. Re: Quartus and source control (continued)
  133. S3 starter kit, command-line
  134. Is necessary to use Modsim on DDR Memory development?
  135. Power Supply Sequencing to V4 MGTs
  136. Open-source JTAG software?
  137. Ultracontroller II: PROM solution in EDK 8.1
  138. Xilinx PowerPC run Program out of SDRAM
  139. FPGA Memory Power
  140. Simple state machine in CUPAL
  141. High rate data transfer from off-chip mem to FSL co-proc...
  142. Low Price Quick turn RoHS pcb prototype manufacturer(NJPCB)
  143. Reset asynchronous assertion synchronous deassertion
  144. SPI c source code to shift register from apex board..
  145. Large Spartan3 vs. Small V5
  146. Webpack ISE simulator error
  147. Alternative for Mentor''s HDL Designer
  148. Spartan 3 Mask Code determination
  149. Bit-Serial Design with Xilinx System Generator
  150. Call for Papers: International MultiConference of Engineers and Computer Scientists IMECS 2007
  151. XILINX XAPP694
  152. IIR filter example ?
  153. Microblaze power estimation with external memory..
  154. chipscope_opb_iba woes in XPS EDK
  155. Crystal input for FPGA
  156. Any interest in a v8 uRISC/Arclite clone?
  157. [Xilinx] MIG V1.6 Reduced max Speed for DDR2 controllers ??
  158. Error building mpmc2
  159. Spartan3 dev board... will USB keyboard work?
  160. RocketIO MGT Tile/Column Question
  161. Video - DSP Eval board with Altera
  162. how to declare a Wishbone interface with 4 bit port size and granularity?
  163. Microblaze : Timingproblems
  164. How to attach module to the design source?
  165. Xilinx Webpack inferring BRAMS, RedHat version
  166. Altera Cyclone-II FIFOs
  167. Arbiter schemes?
  168. Problem of uninstall modelsim
  169. Virtex 4 could not work correct,is it damaged?
  170. Maximum Current Draw of FPGA
  171. dynamic fpga via bytecode sequence?
  172. virtex II inner organisation
  173. Repost: ISE Webpack 8.1 adder wierdness
  174. Xilinx V4FX Embedded MAC.
  175. Call for Papers: World Congress on Engineering 2007
  176. ISE Webpack 8.1 adder wierdness
  177. Gaisler on a Spartan 3E Starter Kit?
  178. Clock domain crossing (again)
  179. EDK: OPB_IPIF, too many versions...
  180. JOP as SOPC component
  181. Dio5 interface with ps2 port
  182. Embedded clocks
  183. (uc)Linux support for Xilinx FPGAs is going to next level
  184. Invoking Cadence NC Sim within Xilinx ISE
  185. consistancy in synthesis/ simulation model
  186. Compiler can't detect std_logic_1164 package
  187. NgdBuild:604 error
  188. Anyone really using Virtex-5 FPGAs yet?
  189. Altera SOPC ModelSim question
  190. synthesis intelligence of quartus regarding range of values
  191. TIG on Xilinx Asynch FIFO?
  192. EDK peripherals and CoreGen netlists
  193. Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
  194. Real-world soft-cpu performance
  195. xst synthesis with attributes failure
  196. Development Board Offers
  197. Unpicking Logical Synthesis
  198. Xilinx PCI Core & CardBus
  199. DSP core, use of real type signals (Altera Stratix)
  200. ISE software bug???
  201. A Newbie question
  202. Newcomer question
  203. Simple code to check out Spartan3 starter kit?
  204. Spartan 3 StarterKit Weirdness
  205. Question about SSTL
  206. Avnet V2Pro dev board "Hello world"
  207. logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw
  208. 100 Mbit manchester coded signal in FPGA
  209. Networking : Multicast Performance
  210. Switching speeds on V4FX RocketIO
  211. New to RocketIO
  212. Re: Microblaze, EDK, Spartan 3 and Webpack
  213. Open source Xilinx JTAG programmer with Digilent USB support
  214. Who is your favourite FPGA guru?
  215. 3.3V configuration of Spartan-3?
  216. WHAT SITUATION I NEED A BUFFER
  217. FPGA : PCI-Xilinx Core, PC not booting
  218. How do I treat "default" case which is useless?
  219. Low Price High quality RoHS lead Free pcb prototype manfuacturer!!
  220. Changing SerDes speed on the V4FX RocketIO
  221. Counter status flags don't stay asserted not sure why?
  222. clock problems with Spartan 3E starter kit
  223. Xilinx Impact USB speed problem
  224. FPGA interface to serial ADC
  225. verilog versus vhdl
  226. Post PAR simulation, type not match
  227. virtex ppclinux files
  228. How to implement large ROM's from binary sources?
  229. checking the FFT cores on Xilinx FPGAs
  230. Synplify
  231. Noob quesion about SDRAM usage.
  232. DDR Controller
  233. Raggedstone1 ADV7202 Module
  234. Xilinx PCI Core burst problem
  235. profiling my application in microblaze...
  236. RocketIO simulation in VCS
  237. Component Instantiation ERROR:HDLParsers:3281 in ISE 8.1i
  238. Xilinx System Generator crashes repeatedly
  239. Xilinx System Generator crashes repeatedly
  240. Microblaze Sierro RTOS is no longer available??
  241. Cyclone I & II memory fmax
  242. Xilinx ISE 8.2 implementation problem
  243. Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released
  244. coming soon: MB 5.0
  245. Coregen help
  246. EDK, user IP, how to use user-functions
  247. In NCVerilog, how do I suppress "$readmem warning: words less than that given by address bounds"?
  248. ASIC Design Engineer Job in SHENZHEN China
  249. How can we fully utilize available BRAMs...
  250. MicroBlaze SPI interrupts