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  1. How to configure Block RAMs with constant values
  2. Impedance I/O SPARTAN3 board
  3. Share BRAM for data and instruction OCM?
  4. Microblaze store
  5. Programming model on FPGA
  6. Software Compile : gcc command not found
  7. EDK: command not found
  8. DSP Library for PPC405?
  9. THERE IS A BETTER LIFE!! MAKE $20 TO $50 THOUSAND DOLLARS IN LESS THAN 60 DAYS!!!
  10. Pipelining can reduce the slice usage
  11. Aurora IP core vs. RocketIO wizard
  12. Influence of temperature and manufacturing to propagation delay
  13. sending data across a 32 bit bus
  14. Why are there ModelSimAltera warning
  15. xilinx_device_details.xml <= which program create it?
  16. FFT in VHDL (or Verilog) Tutorial
  17. problem about license of Modelsim in Altera quartus webpack
  18. xupv2p
  19. Xilinx ML310 programming failure
  20. Running an application from external memory in Xilinx
  21. Nested Generate Statement in VHDL
  22. NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
  23. Compile error by Cadence NC-Sim
  24. IEEE 1149.6 support in Virtex-5
  25. Seemingly random delays on Xilinx OSERDES
  26. FPGA Debug Tool
  27. simulating two-dimensional array in vhdl
  28. How to control the running of NC-Sim and Xilinx ISE under Unix?
  29. regarding changing serial data out to LVDS form
  30. MPMC2: MPMC2 with DDR2 SDRAM
  31. Virtex-4 : OCM
  32. Question about adder structure
  33. Xilinx platform cable USB
  34. Question about Maxplus 2?
  35. Xilinx USB cable - can't install driver
  36. SOPC builder/Nios2: booting from custom NV-RAM
  37. Xilinx XC9500 Jtag instructions?
  38. Pad to Setup, Clock to Pad
  39. Pad to Setup, Clock to Pad
  40. Power-on reset
  41. EDK : path set
  42. SPI module in FPGA
  43. SDRAM of Spartan 3E
  44. EDK post 7.1 Opinions
  45. Virtex-5 Webpack?
  46. replacement for Altera EPCS64
  47. MPMC2 with Virtex-5
  48. Xilinx Chipscope and EDK
  49. "|->" implicate and sequence in SVA?
  50. Quartus download problem?
  51. using FPGAs for synthesizing?
  52. Area Constraints in Xilinx
  53. I look for a wideband SERDES chip
  54. Stratix-III announced
  55. opb_ddr
  56. Over power consumption of APA1000.... What's the problem??
  57. Why 64-bit PLB?
  58. C3188A - 1/3"Digital Output Colour Camera Module
  59. Code for Verilog 8bit * 8bit pipelined multiplier
  60. shaping aynchronous signal
  61. add-compare-select
  62. Xilinx Partition for EDIF Flow (synthesis synplify)
  63. XUP-V2Pro banking rule problem
  64. bidirectional bus
  65. tri0 GSR = glbl.GSR;
  66. Microblaze + uClinux issues
  67. ZBT Bus
  68. ISE bugs or newbie error?
  69. PicoBlaze and (leon) grlib CAN2B core / spartan3E starter kit
  70. drive LVDS clocks with a spartan3
  71. access to EPCS pins on Altera device without using the NiosII processor
  72. abel to vhdl converter
  73. HOT NEW SITE DemandADate-females earn $44 per date/up to $4000 a month
  74. Where can I get a opencore of a fifo with atlantic interface?
  75. Static Power vs. Temperature
  76. pin name misspelling error!
  77. Xilinx ISE ucf management
  78. can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
  79. xilinx spartan timing model
  80. Non deterministic behaviour in quartus II ?
  81. floating point arithemetic on fpga
  82. Nios2 access to EPCS device without using HAL drivers
  83. Field Programmable Object Array
  84. Graphics-2-FPGA
  85. Platform USB Cable and Windows XP Pro x64
  86. problem in interfacing with SDRAM controller
  87. Re: Need just a few 5V Spartan
  88. H for FPGA
  89. problems with using altera vhdl testbench in ModelSim
  90. Upgrading spartan-II: possible?
  91. confused result in Logic Analyser, being crazy...
  92. avalon tristate slave address
  93. How to send data/program to the memory of a Spartan 3 starter kit board
  94. Microblaze FPU and IEEE754 single precision number format
  95. How to generate a PROM file and then burn it on FPGA
  96. Re: FFT help
  97. How to simulate netlist with gated clock?
  98. Should I use an external synthesis tool?
  99. Modelsim problem - mixed VHDL,Verilog & VHO
  100. Chip to Chip LVDS
  101. XUP USB
  102. Once synthesized BRAMs are still vanishing in WebPACK version 8.1and up (version 7 was working!)
  103. ISE/EDK project on a file server?
  104. surprised output of Xilinx Virtex-4
  105. Cypress 68013 - Xilinx FPGA
  106. Global Clocks in Xilinx Virtex-4
  107. PCIe latency
  108. To Xilinx guys out there - microblaze mapping problem
  109. choise of fpga platform
  110. Schifra Reed-Solomon ECC Library
  111. I2C Master in Verilog
  112. WORLDCOMP'07: Call For Papers/Sessions--multiple int'l. conferences in computer science & computer engineering, USA
  113. Formal Logic Equivalent Check (LEC)
  114. Spartan3E kit and BPI configuration problem.
  115. post-synthesis simulation issues with ModelSim
  116. How to transform matlab value to FPGA value
  117. Integration of modules
  118. Integration of modules
  119. Using Altera Nios II Stratix II dev kit just as FPGA.
  120. FSL microblaze to co-processor write problem...
  121. PCI
  122. Cleaning generated files in Xilinx 8.2 EDK and ISE
  123. EDK Modelsim Simulation with RS232 Hook
  124. EDK 8.2i/cygwin issues
  125. maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
  126. Re: DDR_controller_EDK
  127. Conformal compare retiming netlist and RTL
  128. SystemVerilog not use Mail-box directly in VMM and AVM ?
  129. JTAG connection for chipscope
  130. regardign signal assinment statement............................
  131. digilent spartan-3 board sram timing
  132. Scientific Computing on FPGA
  133. Re: Need just a few 5V Spartan
  134. chipscope
  135. reset
  136. Re: DDR_controller_EDK
  137. EDK software development
  138. How to avoid negative slack?
  139. Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
  140. Warning LIT:176, DCM in Virtex 4?
  141. I can not simulate "pipelined divider v3.0"
  142. Quartus synthesising out signals?
  143. Tsamp for Spartan 3?
  144. Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
  145. Re: DSP48 carry logic for multi-precision addition
  146. Dual-port BlockRAM "write first" puzzler...
  147. Need flash adc with plcc format?
  148. Re: XPS Flashwriter tool errors on last location in flash
  149. can someone post or email xusbdfwu.hex (1021) from linux ISE 8.2 webpack
  150. Re: De-serializer using Xilinx DCM
  151. Rad-hard (neutron/SEU and space) tutorial?
  152. Re: Need just a few 5V Spartan
  153. Re: Need just a few 5V Spartan
  154. Re: SPDIF receiver
  155. Re: De-serializer using Xilinx DCM
  156. Re: Spectre of Metastability Update
  157. Question about importing modules to XPS.
  158. Programming Virtex II Pro Eval Board
  159. xilkernel cache
  160. PC configuration for best Xilinx ISE performance
  161. Picoblaze simulation
  162. Taking forever to synthesise (XILINX ISE 8.1i)
  163. Virtex-II Pro CRC Test Data
  164. clock multiplexor device
  165. Dual Port RAM
  166. prob regarding Bitgen failed while gen prog file xilinx ise 7.1i
  167. Stratix to PC communication
  168. image processing
  169. Safe Routing
  170. Spartan3E clk/BUFGMUX warning
  171. SystemVerilog interface: virtual and ref
  172. Hardware mapping of algorithms
  173. Virtex-4 & Wifi
  174. Stratix II basic questions
  175. Question about generic usage?
  176. Usage of RAMB16 prmitives
  177. A spectre is haunting this newsgroup, the spectre of metastability
  178. A spectre is haunting this newsgroup, the spectre of metastability
  179. FPGA-based music synthesizer (with MyHDL)
  180. uBlaze ISR : Steps to write/implement an ISR...
  181. uBlaze Cache: update Cache Instruction...
  182. Survey: simulator usage
  183. connecting SFP-module to Virtex2PRO
  184. EDK 8.2.01i:Spartan3E BSB Problem...
  185. Implementing Direct Memory Access for Peripheral (Xilinx Virtex 2 Pro)
  186. Have you experience to program the APA series using FlashPro Lite?
  187. Xilinx Virtex-4 Clock Multiplexer Inputs
  188. a new spartan3E 1600 starter kit available ?
  189. Chipscope and debugger through the same JTAG port
  190. Xilinx Virtex4 Outputs for Camera Link
  191. Call for Papers: The IAENG International Conference on Electrical Engineering (ICEE 2007)
  192. OPB to SPI clock frequency ratio
  193. Jumps in FPGA implemented integrator
  194. Quartus DSP Blocks
  195. Semantics or examples for Xilinx xgpio driver under Linux?
  196. xilinx sync fifo with first word fall-through
  197. Am I seeing meta-stable or what?
  198. can someone recommend a board?
  199. OT: FPGA soft-core humor
  200. Meta-stable problem with MAX-II ?
  201. Single Bank Vs Multiple Banks in sdram
  202. V5LXT support for ISE released yesterday
  203. Xilinx MIG 1.6 doesn't launch
  204. Supported bus widths for RLDRAM on Virtex4?
  205. Stream cipher
  206. XPS crashes while performing clock DRCs when I have DCR componentsinstantiated
  207. Bit order reversed in Xilinx post-translate simulation
  208. Simple multiply in Xilinx?
  209. What should I do with std.textio.all of ModelSim
  210. Help with SysAce CF
  211. Can I unstantiate IBERT core in a V4FX design?
  212. S3ESK JTAG
  213. Avnet virtex-5 board
  214. Memory
  215. Please Help
  216. ISE 8.2 freeze
  217. microblaze uclinux ping delay
  218. DDR SDRAM access with MPMC2, Databus Width
  219. Memory Replicator
  220. Xilinx Virtex4 DDR clock output
  221. Data2Mem Error Help on dual PPC system
  222. Survey on Quartus SOPC/Nios-II
  223. How to check if ROM got inferred from synth reports
  224. iMPACT:923 - Can not find cable, check cable setup !
  225. Camera link specification
  226. PowerPC somehow unstable at 300 MHz
  227. XC2V80005FF1517C
  228. Microblaze : FSL bus
  229. Spartan 3 Configuration Questions
  230. Call for Papers: IAENG International Conference on Data Mining and Applications ICDMA 2007
  231. How do I erase an Altera EPM7064 with JTAG lockout
  232. Virtex4 debug bitstream generation problem
  233. Where is the XORCY in the synthesised file?
  234. Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
  235. Can ISE text editor generate CRLF line endings?
  236. cross-post: newsgroup servers
  237. Code synthesizes to one FPGA but not to another?
  238. How many clocks are needed for a fastest ADD instruction of latest Intel CPU
  239. Inferring block ram in Spartan II with non standard bus sizes
  240. System ACE and remotely reconfiguring an XUP board?
  241. i486 FPGA replacement
  242. Reversing SPI shift out order on Microblaze design
  243. JTAG pins of the xc2s200E for user I/O
  244. SDF sim failure: 8.2i/Spartan-3
  245. Virtex-5 DSP48 - fun while sick at home
  246. Xilinx PCIe 8-lane endpoint constraints
  247. EDK - XPS 8.1i segmentation
  248. FIR filter generic
  249. A very nice free browser to try...
  250. LIST OF FPGA PRODUCERS AND TOOLS DEVELOPERS