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  1. How to read data from intel strata flash using microblaze?
  2. System ACE PROG_B and INIT pins
  3. @(posedge clk)
  4. Aurora v2.5
  5. How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
  6. approximation of an exponential ramp?
  7. linking two fpga boards
  8. Writing output signals to text file (VHDL)?
  9. Some questions about FFT implementation
  10. impossible opb_emc hack?
  11. Current programming hardware does not support Active Serial programming mode
  12. JTAG programming of Altera Cyclone and CONF_DONE
  13. Using Jtag for general Communications
  14. How to develop custom opb devices for Microblaze?
  15. computer vision projects for open cores
  16. regarding -ve slack while doing post PAR timing analysis
  17. 50 MSPS ADC with Spartan 3 FPGA - clock issues
  18. Barrel shifter in Virtex4?
  19. Query :Regarding Synthesis Report
  20. FFT on Virtex-II Pro (how to download .dat file?)
  21. Xilinx platform flash data sheet confusion (ds123) for clocking
  22. FFT on Virtex II Pro (how to download .dat file?)
  23. Query :Regarding Synthesis Report
  24. Implementing DVI EDID on Stratix II GX?
  25. Call for Papers (extended): International MultiConference of Engineers and Computer Scientists IMECS 2007
  26. Looking for simple Cycone 2 example design
  27. Organization of character bit maps
  28. source synchronous timing (Xilinx)
  29. About Unstable Operation of ACTEL(A3P1000)....
  30. Problem with connecting higher order address lines of SDRAM to FPGA
  31. FPGA : LIFO
  32. query regarding capacitance of pins of cyclone device
  33. About partial reconfiguration in Virtex 4
  34. Recursive component instantiation
  35. testbench help
  36. RTL Hardware design issue: Count Leading Zeros CLZ
  37. FPGA+Ethernet
  38. differential I/O with ISE 8.2 / spartan3E
  39. PlanAhead : problems
  40. regarding -ve slack while doing post PAR timing analysis
  41. Microblaze LMB bus
  42. Quartus II: Back-annotating bidir's gives two entries per pin...
  43. Xilinx PAR crashing with 'make'
  44. Registers initial values with Altera Stratix II
  45. ANNC: SERDES Fundamentals Webcast
  46. FPGA to Camera (Channel) link
  47. XSA3S1000 board and SDRAM
  48. VHDL Variable Length Input file.
  49. VHDL Variable Length Input file.
  50. How to reduce jitter of 30-bit accumulator
  51. Remove DCM wrappers from EDK designs
  52. How to find an FPGA board
  53. How do I delay signal to pad?
  54. help with Xilinx LVDS syntax
  55. Clock phase shift
  56. Xilinx PLB IPIF
  57. EDK 8.2, MDM, and ChipScope....
  58. Timing constraint on DCM input ignored after update ISE 8.1 -> 8.2?
  59. Altera starter kits
  60. query in gate level simulationin quartus s/w 6.0
  61. Timing constraings: min delay?
  62. First Look at QuartusII 6.1
  63. Usage of BUFIO in Virtex 4?
  64. Xilinx MPMC2 "External Ports" question
  65. Virtex-4 ML403 16x2 LCD
  66. RLOC weirdness
  67. How to check high impedance of a RAM with Logic Analyzer
  68. Creating a single logical netlist...
  69. Question concerning XAPP224
  70. Free Anydivider, Divide clock by any number
  71. Spartan-3A launched
  72. Using quartus "In system memory editor" from command line
  73. Readback Jtag Problem
  74. Spartan3 IBIS / Simulation questions
  75. Xilinx EDK/XPS 8.2 freezes XP desktop when launching XMD
  76. Can you configure an Altera Stratix without the nStatus line?
  77. XEM3010
  78. coherent logic
  79. how can I use DCM in paritial reconfiguration design?
  80. Call For Papers/Sessions: WORLDCOMP'07--multiple int'l. conferences in computer science & computer engineering, USA
  81. EDk and DCM
  82. Picoblaze C compiler 1.8.4
  83. Buggy behaviour in Modelsim, when reading from pipe?
  84. Check this out
  85. LUT input order
  86. Funny Videos
  87. Digitally Controlled Impedance with Lattice ECP2M FPGA's
  88. Video Mux using FPGA
  89. Hi
  90. Aurora simplex channel problems
  91. Caching of external memory
  92. Firmware for Xilinx USB cable
  93. EDK 8.2 Busmaster Example
  94. PowerPC_bus
  95. How to save a changed *.wlf file with ModelSim
  96. LVDS output pins of Altera Cyclone II
  97. DCM jitter (again)
  98. Xilinx XPS - OPB - EMC software halts. Someting fishy
  99. Anyone use Xilinx ppc405 profiling tools?
  100. Thesis
  101. Can I see the detail timing parameter by Quartus II tools?
  102. help
  103. Question: TMED Algorithm
  104. Opencores DDR SDRAM controller
  105. wanted: FPGA programmer
  106. Prefetch buffer in microblaze
  107. Old XCell journals gone?
  108. SPI Flash on Avnet Spartan 3E Eval Kit
  109. Spartan-3E or Generic FPGA -> PC133 interface details??
  110. ISE on a cluster?
  111. Stratix II GX Transceivers
  112. modular design / PlanAhead
  113. FPGA application field
  114. XC3020-50 board documentation
  115. FPGA workstation - should I wait for Window Vista?
  116. Bus Lock
  117. DVI clock generation
  118. Hardware in the loop simulation for Altera design
  119. Xilinx XST Incremental Design Change
  120. So who has used Lattice FPGAs recently?
  121. ModelSim Xilinx edition new bug?
  122. Spartan3 Configuration Puzzler
  123. ignore - test post
  124. pre-synthezis simulation in ModelSim for Actel
  125. Xilinx ML555 availability
  126. verilog 2 VHDL translator
  127. Bus structures question (Spartan 3)
  128. Xilinx FIFOs round 2 - BUG-BUG in MPMC2
  129. Digital PLL and FM demodulation
  130. problems with verilog SDRAM models
  131. opb master kills linux?
  132. avnet FX12 mini module example temac design does not work in edk 8.2.02i
  133. What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
  134. What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
  135. nios2 toolchain sources
  136. Microblaze Code and XMP functions
  137. edk evaluation
  138. Altera's USB blaster
  139. playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
  140. Pullups and pulldowns in EDK?
  141. tips for P&R in FPGA(quartus)
  142. I2C Controller implementation
  143. I2C Controller
  144. QPROM in FPGA
  145. query in constraining timing
  146. Mico32, how good is it?
  147. vccaux and vccint
  148. EDK 8.2 STUPID STUPID BUG (minor)
  149. Verilog Ref Book
  150. Xilinx WebPACK 8.2.03i + Linux Problem
  151. Aurora 2.4 error
  152. Dev Kit Shipping Costs
  153. IE7 and ISE Help
  154. playing test SVF files for Spartan-3 Starter Board (using iMPACT ?)
  155. Double buffering
  156. query
  157. query
  158. logic analyzer using FPGA
  159. run a counter without a clock
  160. MPMC2 DDR2 simulation
  161. Verilog problem: default case to set signal xxxx
  162. MicroBlaze & top module?
  163. Altera MAX3000A OE and GCLR-Pins
  164. jtag loader for picoblaze
  165. types of FPGA
  166. For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
  167. Are FPGAs available with ADCs onchip ?
  168. What's Nonpipelined bus mean?
  169. Xilinx EDK Problem
  170. Constraining timing analyser when using two DCMs
  171. Voltage prorating for Spartan 3
  172. DCM Jitter
  173. Problems connecting MicroBlaze to custom IP
  174. C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
  175. query
  176. Altera configuration with microcontroller
  177. Division of a (rather large) Gate level Combinational Design
  178. Cache trouble in XPS
  179. Cache trouble in Xilinx XPS
  180. Aurora and Chipscope
  181. Virtex 4 Internal Tristate (BUFT)?
  182. Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
  183. Xilinx DDR2 IP core performance
  184. Protecting netlist for Xilinx
  185. ISE 8.2 & XC9500XL family
  186. CORDIC FM Demodulation
  187. I2C "READ" Setup/Hold Requirement
  188. Spartan 3E-Kit
  189. V5 LXT PCIe Block simulation
  190. Spartan-3E Starter Kit and programmable pre-Amplifier
  191. timing constraints
  192. timing constraints
  193. What's wrong with my tcl example in Quartus?
  194. Missing module : XFFT_V3_1 Verilog (not VHDL) module
  195. Spartan 3 Starter Kit .mcs upload problem
  196. DDR_SDRAM_VHDL_models
  197. DDR_VDHL_models
  198. ISE Synthesize Properties box
  199. Parallax Stratix Smartpack accessories?
  200. Differential to single ended convertion in FPGA
  201. Spartan3E price update ?
  202. Need examples/instruction: use of altpll_reconfig (Altera)
  203. Simple questions on IDELAYCTRL
  204. Input setup time & Hold Input
  205. Q on duty cycle
  206. false path
  207. query in delay chains
  208. Spartan-3E slice resources
  209. Virtex-4 DDR RAM Usage (with VHDL)
  210. spartan-3e starter kit and ethernet
  211. Call for Papers: The International MultiConference of Engineers and Computer Scientists IMECS 2007
  212. EDK 8.2 Block RAM error
  213. master support for OPB device
  214. IDELAY setup/hold
  215. Static Timing Analysis vs Dinamic Timing Analysis
  216. Input setup time & Output valid delay
  217. IDELAY Calibration - Virtex 4
  218. Re: How stable is the internal clock of a Xilinx CPLD?
  219. Re: FPGA's for Ethernet?
  220. query in a design
  221. state problems with Quartus II 6
  222. PCMCIA interface
  223. How could the 'Serial write time out' happen
  224. pulse jitter due to clock
  225. ML405: Board support package
  226. memory init in Altera bitfiles, (like data2mem) is it possible?
  227. FPGA board
  228. combinatorical divide by 2 in FPGA
  229. How to use "ON NBC 12429" as clock resource of Virtex-4
  230. Hpw to remove combinational loops in quartus s/w
  231. xsa-200 building a Mp3 player
  232. Spartan 3/3E to Standard TTL/Low power devices
  233. Validity of data on rising edge of clock
  234. Warnings in Xilinx 8.2i
  235. Maximum Operating Frequency
  236. Synthesis size of Circuits?
  237. V-5 power saving ...how?
  238. use boundary scan in spartan-3
  239. Compiling Linux Kernel for ML405
  240. ise 7.1
  241. USB and AHB
  242. Problems with Opencores' I2C "READ" function
  243. how to filter glitches and mutliple transitions?
  244. 8080 FSGA model in an FPGA
  245. Xilinx 2 DCMs with delay on lock
  246. XCF02S + Spartan 2e JTAG config problems
  247. Getting Xilinx DMA SG working with peripheral
  248. Old Spartan-II, worth prototyping?
  249. VCD (value change dump) files
  250. Synopsys VCS for Windows