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  1. Call for Papers: The2007 International Conference of Electrical and Electronics Engineering (ICEEE 2007)
  2. Gigabit Ethernet UDP/IP
  3. SDK 8.2 error 127
  4. Call for Papers: The2007 International Conference of Computational Statistics and Data Engineering (ICCSDE 2007)
  5. IDELAY and whether pigs can fly...
  6. Will FPGAs suit my need?
  7. How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
  8. XST bug inferring dynamic shift register
  9. FIFO LogiCore with ISE 8.2 ??
  10. Stratix RAM limitations
  11. Too many warnings in Modelsim?
  12. xc3sprog
  13. XMD with Microblaze and EDK 8.2
  14. 16-bit DDR memory controller in EDK
  15. user constraint file of slice based bus macro in virtex 4
  16. arbitrator
  17. Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
  18. RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
  19. Xilinx Synchronous FIFOs
  20. picoblaze RS-232 using 62.5 MHz
  21. Interlock and stall in CPU design?
  22. Quick question on Coolrunner II IO voltages
  23. EDIF generation from C
  24. altera MAX II dev kit LCD mountings??
  25. Santa Clara Connector and LVTTL etc
  26. Transport Delays in Modelsim
  27. inserting text into a video stream (from a pre-existing video source)
  28. Can I use 3.3V clock into the MGTCLK? MGT RocketIO
  29. LWIP EXAMPLE??
  30. Is this Multi-Cycle Path ?
  31. VHDL Model of a stepper motor
  32. P160 analog module ?
  33. crossing clock domain ??
  34. Operate Flash S29GL-N from Spansion
  35. ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
  36. Is the FSL a good approach for this...?
  37. PCI-Express TLP example
  38. Delaying signal
  39. Possibility of 80188 VHDL core
  40. V4FX PPC data cache behaviour?
  41. crash of xilinx fpga_editor
  42. Accessing SATA hard disk for read/write IO through FPGA in an embedded environment
  43. Quartus II 6.1 Remove Duplicate Logic option removed
  44. Variable clock using Virtex 4?
  45. Generate ACE File: *.elf does not contain start address
  46. MI5 Persecution: Dirk Gently on the Toronto Case
  47. MI5 Persecution: Security Service Tribunal Denies
  48. CREATE FPGA-PC CONNECTION (LWIP, XILNET)
  49. (-1)*xn operation in FPGA
  50. Use Multi-cycle Path or Pipeline?
  51. Build an FPGA programmer cable
  52. First Picture of Craignell Modules
  53. Basic questions about digital phase locked loop
  54. how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
  55. Is there a simple complex magnitude algorithm in FPGA implementation?
  56. Does Modelsim XE support coreconnect BFM simulation?
  57. email protection in the list
  58. Problem with unused pin on Spartan 2E
  59. query
  60. data transfer from fast APB clock domain.
  61. Help Implementing an 1000Base-T Ethernet on Stratix II GX
  62. Xilinx 2-D DCT core (Where?).
  63. Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
  64. Anyone seen eASIC?
  65. timing constraints properly setup
  66. WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
  67. dynamically created blockRAM contents?
  68. Spartan3E minimum clock-to-output (hold time)
  69. Altera Cyclone II die revision?
  70. ISE 8.2sp3 clobbering source file timestamps?
  71. LatticeMico32 Problem
  72. Unconnected Blocks??
  73. Virtex 4 FIFO question
  74. MI5 Persecution: Communications with Security Service Tribunal in 1999
  75. iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
  76. measure setup and hold time
  77. [XST 8.2.3] DSP48 inference multiply/add
  78. MI5 Persecution: Eye Say, and Lord Gnome Answers
  79. DC timing violation, what to do first?
  80. MI5 Persecution: Counter-surveillance sweep by Nationwide Investigations Group
  81. FPGA ROUTING
  82. Mapper using wrong EMAC with PowerPC in V4FX60
  83. newbie needs help
  84. Chipscope
  85. xilinx spi example under linux
  86. Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
  87. Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
  88. PPC cache errata
  89. FPGA-CPU THROUG ETHERNET
  90. Wishbone I2C Application
  91. EDK 8.2 bidir gpio in XBD (board definition)
  92. Xilinx: Connecting an on-chip memory-like component to Microblaze
  93. ISE Simulator radix question
  94. Strange JTAG TCK problems with Spartan XC3S400
  95. lead free bga pads
  96. Bitstream programming
  97. Surface mount ic's
  98. PPC PLB <=> FPGA fabric
  99. help on Xilinx USB download cable
  100. KO mafia ! Global Democracy TRIVOLUZIONE ARTSENU COLD FUSION W post OPEC
  101. Help with ISE (multi-source in unit error)
  102. xilinx xc9536?
  103. hi......
  104. Memory controller design
  105. How to deal with the negative value
  106. ERROR:NgdBuild:604
  107. (Improve Verilog skill) Recommend CPU core with good document and coding?
  108. Tools available to split the design into multiple FPGAs.
  109. SUNDANCE FPGA CONFIGURATION
  110. For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
  111. SPI slave problem
  112. system ace - ERROR: IMPACT:477 - what is this?
  113. Visual IP Designer
  114. Visual IP Designer
  115. ChipScope - impact on design or not?
  116. remove logic redundancy
  117. ethernet checksum nightmare
  118. Why AHDL didn't catch on like Verilog or VHDL?
  119. assigned a special pins in ISE
  120. SystemVerilog Sequence Coverage Problem?
  121. Problem in Xilkernel
  122. Impact with non-standard LPT base addresses
  123. moving from xlinx 8.1 to 8.2 or better wait ?
  124. better ways for debugging?
  125. Judge complex degree by state numbers?
  126. Last Call for Papers: International MultiConference of Engineers and Computer Scientists (IMECS 2007)
  127. OPB master implementation
  128. Need Recommandation for DDR2 controller virtex4
  129. mobius, from codetronix, anyone has been tested
  130. Signal <foo> is assigned but never used. XST Warning help
  131. Matlab (.m) to VHDL
  132. max II dev kit pin grid
  133. PicoChristmas - 112 Free PicoBlaze KCPSM based MicroFpga's released
  134. IEEE fixed-point package FATAL_ERROR
  135. Embedded Development Tools
  136. Help with xilinx simulation?
  137. FSL feasibiliity
  138. DCM start up
  139. What next next big thing coming for HDL?
  140. How to simulate from the xilinx ISE
  141. Call for Papers: The 2007 International Conference of Computational Intelligence and Intelligent Systems (ICCIIS)
  142. XILKERNEL and MICROBLAZE (how to probe this)
  143. a good blog on digital electronics
  144. Embedded Development Tools
  145. timing?
  146. Soft processor Microblaze vs embedded core PowerPC
  147. nets not recognised
  148. New user help required
  149. Manually creating a LUT in VHDL
  150. A nice CIC-Filter, but I can't find the result in the bitsequence!?
  151. CCLK Virtex4 IBIS model.
  152. MICROBLAZE AND OPB: TOO SLOW FOR VGA
  153. CPLD speed/temperature equivalent
  154. Tracing UNKNOWN drivers
  155. Tracing UNKNOWN drivers
  156. Call for Papers: The 2007 International Conference of Applied and Engineering Mathematics (ICAEM)
  157. Spartan 3E Starter Kit Woes
  158. Board for sale
  159. Dynamic DCM Controller help
  160. Need book for verilog on xc9536?
  161. Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
  162. Dynamic DCM Controller help
  163. Dynamic DCM Controller help
  164. ANN: PicoBlaze C: compile to bitstream!
  165. PowerPC_simulation
  166. interrupt handling using microblaze with XPS
  167. PLL minimum input clock frequency
  168. dcf file format
  169. Xilinx Quiz: 150/3 = ?
  170. words of the day
  171. Integrating Atera “FFT MegaCore Function” in Mentor FPGA Advantage 7.2
  172. C2H problems
  173. Operate on RAM through FPGA
  174. jtag reset seq
  175. Call for Papers: The World Congress on Engineering WCE 2007 (IAENG conferences with Engineering Letters)
  176. Frequency divider ?
  177. FX12 ethernet resource usage
  178. incremental compiles in quartus
  179. FX12 ethernet resource usage
  180. Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
  181. OFFSET Constraining a Signal behind a DCM?
  182. unexplainable Problem on Spartan 3
  183. unpredictable FPGA behaviour
  184. VHDL CODE FOR SDRAM IN SPARTAN 3E
  185. Call for Papers (extended): IMECS 2007 (IAENG conferences)
  186. solder mask for fpga dissipation
  187. ppc elf data and vectors sections
  188. ERROR:MDT - ERROR FROM TCL:- linux_mvl31 ()
  189. EDK, header file modified and problem
  190. Frequency divider?
  191. DSP or FPGA for high-speed image processing?
  192. PowerPC_EDK to ISE
  193. Netlist Simulation for PPC (Virtex-4 FPGA)
  194. Re: electrical level conversion
  195. Xilinx PMCD+DCM reset question...
  196. Xilinx WebPack 8.2.03i: can't make .bit file when memories used in design
  197. 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
  198. uClinux bootloader on Spartan-3e Starter Kit
  199. Xilinx ISE 8.2.3 - Re-Creating Projects
  200. Xilins ISE Re-Creating Projects
  201. Xilins ISE Re-Creating Projects
  202. Xilinx ISE 8.2.3 - Re-Creating Projects
  203. Xilinx ISE 8.2.3 - Re-Creating Projects
  204. Re: electrical level conversion
  205. Lcd Block Diagram - Vhdl - On Fpga.. help!
  206. Resource estimation
  207. Query
  208. gtkwave 3.0.18 for win32
  209. Xilinx SYSTEM_JITTER, INPUT_JITTER Questions - Part II
  210. Using SYSTEM_JITTER and INPUT_JITTER for timing analysis.
  211. Adding Jitter
  212. Virtex-II Pro: Reading/Writing data with Compact Flash
  213. Virtex-II Pro: Reading/Writing data with Compact Flash
  214. Virtex-V MGT SONET alignment
  215. Port OS: Error when generate the Libraryies and BSPs
  216. How to get ISE to create a _bd.bmm file for BRAM initialization
  217. SDRAM in SPARTAN 3E
  218. query
  219. CMI Coder/ Decoder
  220. How does FPGA tools infer FIFO
  221. Complex mixer
  222. GUI Based vs. Manual Instantiation of Components
  223. more of ERROR:MapLib:661
  224. Ones' complement addition
  225. Maplib Error 661.
  226. what are your current SoC design for ?
  227. Energy consumption estimation of Virtex-4
  228. MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
  229. IQ multiplier
  230. electrical interface problem LVPECL - LVDS multi-inputs
  231. NOR Flash Controller
  232. BLVDS_25 @ SPARTAN3
  233. Call for Papers: World Congress on Engineering (WCE 2007)
  234. FPGA : Async FIFO, Programmable full
  235. ANNC: Static Timing Analysis Webcast
  236. Next Xilinx starter Kit
  237. ISP interface
  238. Camera Link to XUP V2Pro Board
  239. . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
  240. Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
  241. booting from isocm
  242. Virtex4 : cleaner signals?
  243. config prom power
  244. Tarfessock1
  245. Partial reconfiguration
  246. DDR2 DIMM memory termination resistors?
  247. Give me job :)
  248. spartan3E : which differential inputs level fits CAN2B bus level ?
  249. ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
  250. Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)