- Call for Papers: The2007 International Conference of Electrical and Electronics Engineering (ICEEE 2007)
- Gigabit Ethernet UDP/IP
- SDK 8.2 error 127
- Call for Papers: The2007 International Conference of Computational Statistics and Data Engineering (ICCSDE 2007)
- IDELAY and whether pigs can fly...
- Will FPGAs suit my need?
- How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
- XST bug inferring dynamic shift register
- FIFO LogiCore with ISE 8.2 ??
- Stratix RAM limitations
- Too many warnings in Modelsim?
- xc3sprog
- XMD with Microblaze and EDK 8.2
- 16-bit DDR memory controller in EDK
- user constraint file of slice based bus macro in virtex 4
- arbitrator
- Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
- RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
- Xilinx Synchronous FIFOs
- picoblaze RS-232 using 62.5 MHz
- Interlock and stall in CPU design?
- Quick question on Coolrunner II IO voltages
- EDIF generation from C
- altera MAX II dev kit LCD mountings??
- Santa Clara Connector and LVTTL etc
- Transport Delays in Modelsim
- inserting text into a video stream (from a pre-existing video source)
- Can I use 3.3V clock into the MGTCLK? MGT RocketIO
- LWIP EXAMPLE??
- Is this Multi-Cycle Path ?
- VHDL Model of a stepper motor
- P160 analog module ?
- crossing clock domain ??
- Operate Flash S29GL-N from Spansion
- ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
- Is the FSL a good approach for this...?
- PCI-Express TLP example
- Delaying signal
- Possibility of 80188 VHDL core
- V4FX PPC data cache behaviour?
- crash of xilinx fpga_editor
- Accessing SATA hard disk for read/write IO through FPGA in an embedded environment
- Quartus II 6.1 Remove Duplicate Logic option removed
- Variable clock using Virtex 4?
- Generate ACE File: *.elf does not contain start address
- MI5 Persecution: Dirk Gently on the Toronto Case
- MI5 Persecution: Security Service Tribunal Denies
- CREATE FPGA-PC CONNECTION (LWIP, XILNET)
- (-1)*xn operation in FPGA
- Use Multi-cycle Path or Pipeline?
- Build an FPGA programmer cable
- First Picture of Craignell Modules
- Basic questions about digital phase locked loop
- how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
- Is there a simple complex magnitude algorithm in FPGA implementation?
- Does Modelsim XE support coreconnect BFM simulation?
- email protection in the list
- Problem with unused pin on Spartan 2E
- query
- data transfer from fast APB clock domain.
- Help Implementing an 1000Base-T Ethernet on Stratix II GX
- Xilinx 2-D DCT core (Where?).
- Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
- Anyone seen eASIC?
- timing constraints properly setup
- WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
- dynamically created blockRAM contents?
- Spartan3E minimum clock-to-output (hold time)
- Altera Cyclone II die revision?
- ISE 8.2sp3 clobbering source file timestamps?
- LatticeMico32 Problem
- Unconnected Blocks??
- Virtex 4 FIFO question
- MI5 Persecution: Communications with Security Service Tribunal in 1999
- iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
- measure setup and hold time
- [XST 8.2.3] DSP48 inference multiply/add
- MI5 Persecution: Eye Say, and Lord Gnome Answers
- DC timing violation, what to do first?
- MI5 Persecution: Counter-surveillance sweep by Nationwide Investigations Group
- FPGA ROUTING
- Mapper using wrong EMAC with PowerPC in V4FX60
- newbie needs help
- Chipscope
- xilinx spi example under linux
- Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
- Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
- PPC cache errata
- FPGA-CPU THROUG ETHERNET
- Wishbone I2C Application
- EDK 8.2 bidir gpio in XBD (board definition)
- Xilinx: Connecting an on-chip memory-like component to Microblaze
- ISE Simulator radix question
- Strange JTAG TCK problems with Spartan XC3S400
- lead free bga pads
- Bitstream programming
- Surface mount ic's
- PPC PLB <=> FPGA fabric
- help on Xilinx USB download cable
- KO mafia ! Global Democracy TRIVOLUZIONE ARTSENU COLD FUSION W post OPEC
- Help with ISE (multi-source in unit error)
- xilinx xc9536?
- hi......
- Memory controller design
- How to deal with the negative value
- ERROR:NgdBuild:604
- (Improve Verilog skill) Recommend CPU core with good document and coding?
- Tools available to split the design into multiple FPGAs.
- SUNDANCE FPGA CONFIGURATION
- For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
- SPI slave problem
- system ace - ERROR: IMPACT:477 - what is this?
- Visual IP Designer
- Visual IP Designer
- ChipScope - impact on design or not?
- remove logic redundancy
- ethernet checksum nightmare
- Why AHDL didn't catch on like Verilog or VHDL?
- assigned a special pins in ISE
- SystemVerilog Sequence Coverage Problem?
- Problem in Xilkernel
- Impact with non-standard LPT base addresses
- moving from xlinx 8.1 to 8.2 or better wait ?
- better ways for debugging?
- Judge complex degree by state numbers?
- Last Call for Papers: International MultiConference of Engineers and Computer Scientists (IMECS 2007)
- OPB master implementation
- Need Recommandation for DDR2 controller virtex4
- mobius, from codetronix, anyone has been tested
- Signal <foo> is assigned but never used. XST Warning help
- Matlab (.m) to VHDL
- max II dev kit pin grid
- PicoChristmas - 112 Free PicoBlaze KCPSM based MicroFpga's released
- IEEE fixed-point package FATAL_ERROR
- Embedded Development Tools
- Help with xilinx simulation?
- FSL feasibiliity
- DCM start up
- What next next big thing coming for HDL?
- How to simulate from the xilinx ISE
- Call for Papers: The 2007 International Conference of Computational Intelligence and Intelligent Systems (ICCIIS)
- XILKERNEL and MICROBLAZE (how to probe this)
- a good blog on digital electronics
- Embedded Development Tools
- timing?
- Soft processor Microblaze vs embedded core PowerPC
- nets not recognised
- New user help required
- Manually creating a LUT in VHDL
- A nice CIC-Filter, but I can't find the result in the bitsequence!?
- CCLK Virtex4 IBIS model.
- MICROBLAZE AND OPB: TOO SLOW FOR VGA
- CPLD speed/temperature equivalent
- Tracing UNKNOWN drivers
- Tracing UNKNOWN drivers
- Call for Papers: The 2007 International Conference of Applied and Engineering Mathematics (ICAEM)
- Spartan 3E Starter Kit Woes
- Board for sale
- Dynamic DCM Controller help
- Need book for verilog on xc9536?
- Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
- Dynamic DCM Controller help
- Dynamic DCM Controller help
- ANN: PicoBlaze C: compile to bitstream!
- PowerPC_simulation
- interrupt handling using microblaze with XPS
- PLL minimum input clock frequency
- dcf file format
- Xilinx Quiz: 150/3 = ?
- words of the day
- Integrating Atera “FFT MegaCore Function” in Mentor FPGA Advantage 7.2
- C2H problems
- Operate on RAM through FPGA
- jtag reset seq
- Call for Papers: The World Congress on Engineering WCE 2007 (IAENG conferences with Engineering Letters)
- Frequency divider ?
- FX12 ethernet resource usage
- incremental compiles in quartus
- FX12 ethernet resource usage
- Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
- OFFSET Constraining a Signal behind a DCM?
- unexplainable Problem on Spartan 3
- unpredictable FPGA behaviour
- VHDL CODE FOR SDRAM IN SPARTAN 3E
- Call for Papers (extended): IMECS 2007 (IAENG conferences)
- solder mask for fpga dissipation
- ppc elf data and vectors sections
- ERROR:MDT - ERROR FROM TCL:- linux_mvl31 ()
- EDK, header file modified and problem
- Frequency divider?
- DSP or FPGA for high-speed image processing?
- PowerPC_EDK to ISE
- Netlist Simulation for PPC (Virtex-4 FPGA)
- Re: electrical level conversion
- Xilinx PMCD+DCM reset question...
- Xilinx WebPack 8.2.03i: can't make .bit file when memories used in design
- 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
- uClinux bootloader on Spartan-3e Starter Kit
- Xilinx ISE 8.2.3 - Re-Creating Projects
- Xilins ISE Re-Creating Projects
- Xilins ISE Re-Creating Projects
- Xilinx ISE 8.2.3 - Re-Creating Projects
- Xilinx ISE 8.2.3 - Re-Creating Projects
- Re: electrical level conversion
- Lcd Block Diagram - Vhdl - On Fpga.. help!
- Resource estimation
- Query
- gtkwave 3.0.18 for win32
- Xilinx SYSTEM_JITTER, INPUT_JITTER Questions - Part II
- Using SYSTEM_JITTER and INPUT_JITTER for timing analysis.
- Adding Jitter
- Virtex-II Pro: Reading/Writing data with Compact Flash
- Virtex-II Pro: Reading/Writing data with Compact Flash
- Virtex-V MGT SONET alignment
- Port OS: Error when generate the Libraryies and BSPs
- How to get ISE to create a _bd.bmm file for BRAM initialization
- SDRAM in SPARTAN 3E
- query
- CMI Coder/ Decoder
- How does FPGA tools infer FIFO
- Complex mixer
- GUI Based vs. Manual Instantiation of Components
- more of ERROR:MapLib:661
- Ones' complement addition
- Maplib Error 661.
- what are your current SoC design for ?
- Energy consumption estimation of Virtex-4
- MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
- IQ multiplier
- electrical interface problem LVPECL - LVDS multi-inputs
- NOR Flash Controller
- BLVDS_25 @ SPARTAN3
- Call for Papers: World Congress on Engineering (WCE 2007)
- FPGA : Async FIFO, Programmable full
- ANNC: Static Timing Analysis Webcast
- Next Xilinx starter Kit
- ISP interface
- Camera Link to XUP V2Pro Board
- . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
- Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
- booting from isocm
- Virtex4 : cleaner signals?
- config prom power
- Tarfessock1
- Partial reconfiguration
- DDR2 DIMM memory termination resistors?
- Give me job :)
- spartan3E : which differential inputs level fits CAN2B bus level ?
- ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
- Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)