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  1. question about DCM in virtex5: fails the maximum period check
  2. CLOCK GENERATOR
  3. substracting a whole array of values at once
  4. chipscope + mdm with microblaze ..
  5. ModelSim - Do Files
  6. Stereo 3D photography capture stereoscopic still and motion images
  7. Xilinx Ethernet MAC - working with DMA (EDK)
  8. NGDBuild error
  9. Call for Papers Reminder: The2007 International Conference of Computer Science and Engineering (ICCSE 2007)
  10. Disabling Interrupts/Context switching in Xilkernel
  11. Xilinx ML40x SRAM to/from Flash
  12. regarding the usage of tri mode EMAC on virtex 4
  13. uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING )
  14. Applications under MontaVista Linux on ML310
  15. Setting VHDL standard in Xilinx ISE
  16. Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
  17. Digital AM/FM Receiver
  18. Question Regarding Look-Up Tables and Access Time/Levels of Logic
  19. FSL Questions
  20. Do you want to work in a highly complex FPGA/DSP product group?
  21. Need advice to help improve timing on V4 FX
  22. Read CLB information from NCD file
  23. DCT/IDCT on FPGA
  24. Virtex 4 SATA redux
  25. Radar pulse detection
  26. ISE 9.1 sp1 and EDK 8.2 sp2
  27. Interrupts and PPC/opb_intc
  28. Floorplanning with Altera APEX20KE device
  29. question abt DPRAM
  30. question abt DPRAM
  31. Call for Papers Reminder: World Congress on Engineering WCE 2007
  32. Replacing/emulating an asynchronous FIFO
  33. I have discovered the secret of the soul
  34. Parallelism in HDL
  35. Multiple Micorblaze instantion problem solved, Facing debugging related problem.
  36. EDK and multipleprocessors - Virtex2p
  37. Altera ByteBlaster and SignalTap on Fedora Core
  38. Parameter File in Mixed Mode Designs
  39. Impact of only one bank powered?
  40. Actel FIFO in Synplify: blackbox is missing a user supplied timing model
  41. test UART
  42. Questions about pci transactions in my core
  43. Compile uCLinux for Spartan 3e
  44. Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
  45. Call for Papers: The World Congress on Engineering and Computer Science WCECS 2007
  46. question about power dissipation
  47. Spartan-3E starter kit : trouble with configuration from NOR Flash
  48. Multiple MicroBlaze based Multiprocessor system
  49. Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
  50. For Sale: 234 pieces Philips / Xilinx P3Z22V10-BA Zero-Power PLD
  51. ANNC: FPGA Video Interfacing Fundamentals Webcast
  52. regarding the usage of embedded ethernet MAC on Virtex4
  53. generating VHDL code from Matlab code for DSP - wavelet image compression
  54. Xilinx Virtex5 board
  55. HI guys...about EDK
  56. [Q]: Is Digilent still in business ???
  57. CFP; deadline extended
  58. moving data from slower to faster clock domain
  59. 9.1i in Red Hat Enterprise Linux AS 64-bit
  60. or1k on spartan 3, 400K gate version
  61. xilinx x2pro ppc custom crt0
  62. problem with microblaze gcc toolchain
  63. DFT Details....
  64. SystemC hangs abruptly
  65. BFM and Verilog custom IP
  66. query in P&R of FPGA
  67. Reconfiguration
  68. data OCM BRAM Issues
  69. Xilinx Interconnects/Routing
  70. circle generation algorithm
  71. ISE 9.1 SAY YOURS OPINION
  72. XST broken for XC9536?
  73. ProAsic-plus PLL
  74. DDR SDRAM controller for virtex 2 pro
  75. read fpga
  76. EDK tri-state control
  77. Xilinx (without init value) has a constant value of 0?
  78. Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
  79. Webpack 9.1 problems with Impact on parallel cable
  80. Condition Variable in pthread.h
  81. PCI Express user group
  82. Altera DSP Builder
  83. Xc2v6000 package for ise
  84. I uncover the secret of visual consciousness
  85. plb_gemac SerDes mode on V4-FX?
  86. EDA course development
  87. EDA course development
  88. virtex4 configuration via XCF32P Prom
  89. Question about simple design
  90. Where is help for schematic entry?
  91. Synthesis of DSP algorithms
  92. DDR FPGA Design
  93. cpld version?
  94. Graphics demo using FPGA?
  95. UNKNOWN Processor Version (0) in XMD
  96. ahdl --> vhdl
  97. Help with Xilinx i/o constracint for ps/2 port
  98. how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
  99. How to use the test bench wave form simulator?
  100. help with Design Compiler -> Quartus
  101. XUP Virtex-II Pro
  102. Differential pairs per Bank
  103. 1 Gbps - state of the art?
  104. Initialisation of two dimensional array to known non-zero values in verilog
  105. linuxppc on ML403
  106. FPGA : Jobs required
  107. CS conference ranking reference at www.conference-ranking.net
  108. Linux on Virtex 4?
  109. Change ROM contents, .bit file
  110. Xilinx Timing Constraints and failures
  111. USB 2.0 Streaming using FPGAs
  112. Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
  113. DCM instantiation in XPS7.1i and ISE7.1. Bug or error?
  114. Global Clocks in Xilinx ISE
  115. question about DCM usage in virtex 5
  116. Conversion from Xilinx ISE 7 to 8 fails
  117. bram can't store elf
  118. virtex-II DCM phase shift problems
  119. Problem with verilog program
  120. Problem with pin assign using CASE
  121. Problem with pin assign using CASE
  122. How to make an internal signal embedded deep in hierarchy to a gloal output signal
  123. Minimal design for xilinx?
  124. Rank order filtering - XAPP953 - what am I doing wrong?
  125. Higher studies
  126. Anyone have a Lancelot card for sale?
  127. Webpack-9.1 working on debian / grml
  128. Forcing a LUT to not be optimized
  129. Timing analyzer with Virtex 4
  130. Inferring Xilinx RAM's with Byte enable options
  131. how do you code this?
  132. unsigned and signed data in Verilog?
  133. Datapath design problem?
  134. Timing Diagram Tool
  135. ModelSim Leaf Instances
  136. Can't assign pins in Webpack 8.2i schematic design
  137. Porting MontaVista Linux on ML403
  138. Porting MontaVista Linux on ML403
  139. MI5 Persecution: Surveillance methods 5/8/95 (5919)
  140. MI5 Persecution: But why? 2/8/95 (5014)
  141. OrCAD symbol for the Xilinx V5LX50 FF676 device
  142. MI5 Persecution: Truth or Troll? 13/5/95 (3204)
  143. MI5 Persecution: Recognition by Strangers is Normal 12/5/95 (2299)
  144. MI5 Persecution: A doubting Thomas is heard 9/5/95 (1394)
  145. MI5 Persecution: BBC's Hidden Shame 4/5/95 (489)
  146. MI5 Persecution: Newsgroup members join in the discussion (2299)
  147. MI5 Persecution: Intelligence agency sources on the Web (1394)
  148. MI5 Persecution: Toronto Freenet supports free speech (489)
  149. Xilinx USB download cable
  150. xilinx 8.2 xps debug problems
  151. Simulation of DCM with Xilinx 8.2 and Modelsim 6.1
  152. EDK-Modelsim XE
  153. Any UK mirror for ISE 8.2i SP2?
  154. IP Protection
  155. On-chip randomness (V4FX)
  156. CONDITION VARIABLES IN XILKERNEL
  157. virtex II pro development board(xupv2p) : maximum current driving strength from hirose connector
  158. General Number Field Sieve in FPGA
  159. Aligning data with clock
  160. ML403 board - VGA schematics - wrong pins
  161. video buffering scheme, nonsequential access (no spatial locality)
  162. Does xiling cpld's need a power supply bypass cap?
  163. FPGA clock gating ? Or how to avoid it in this case ?
  164. book recommendation for self study in digital logic design
  165. How to make a clock delay?
  166. Platform Cable USB & Windows 2003 Server
  167. uClinux on Spartan 3
  168. ethernet MAC and switch
  169. CFP: CEC2007 Special session on: Evolutionary Computation for EDA
  170. Xilinx Constraints Editor doesn't work anymore?
  171. ANNC: Serial RapidIO Webcast
  172. NIOS II Application startup issues
  173. Good hardware design code re-use strategies, reference book
  174. FPGA damage from bad bitstream
  175. Xilinx plb ipif read fifo
  176. FPGA power supply design
  177. iMPACT dont shows erase write options with fpga
  178. XdmHelpers:662
  179. low speed USB interface for FPGAs
  180. Call for Papers: World Congress on Engineering WCE 2007
  181. Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
  182. Xilinx ISE 8.2
  183. Scrambling for Lattice SC
  184. Xilinx doing a re-entry in non-volatile FPGA arena!!!
  185. Clock constraints
  186. what happened to modular design in ISE9
  187. Call for Papers: The2007 International Conference of Parallel and Distributed Computing (ICPDC 2007)
  188. "Divide" a video line in two stripe
  189. Using demo IP libraries?
  190. How to exclude timing violations in Xilinx *.ucf file
  191. how to use register to save data
  192. When do I need reset and clear?
  193. system generator from Xilinx
  194. project help
  195. digilent nexys vga glitches
  196. suggest me the right fpga
  197. Correction for hwicap_v1_00_a code
  198. How can I make xst to infer BlockRAM instead of Distributed RAM
  199. Final call for papers: Multi-conference
  200. Altera EP2S60 rebooting itself
  201. SPARC V7 CORE
  202. NetBSD on Xilinx fpga (ported to ML403)
  203. Series DCM's and total Lock Time
  204. Call For Papers: WORLDCOMP'07: conferences in computer science & computer engineering, USA
  205. Phasse Detector
  206. Im Hoping This Is What You Need
  207. FPGA implementation of UHF transmitter in airborne applications
  208. Timing Delay Definitions
  209. MI5 Persecution: what people said (4031)
  210. MI5 Persecution: 20,000 Reward (3189)
  211. MI5 Persecution: Website Index (2290)
  212. MI5 Persecution: Hotchkies FAQ (1388)
  213. "Gate" = ???
  214. MI5 Persecution: Dirk Gently on the Toronto Case (489)
  215. Beginner VHDL questions
  216. ISE Simulator Error 222: SuSE 10.1 Linux
  217. Different Modelsim versions disagree in same backannotation!
  218. TESTAPP_PERIPHERAL FAILED IN ETHERNET
  219. Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
  220. Xilinx website login problems
  221. Generation of Divided-by-3 clock
  222. ARM AHBA 1Kbyte boundary issue
  223. Behavior of REV input in Virtex2 flops?
  224. Process on both edges
  225. Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
  226. PCI Card with FPGA
  227. Ethernet Interface
  228. Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently inuse
  229. running applications from external memory
  230. Clock Frequency
  231. interesting article FPGA routing field programmable nanowire interconnect(FPNI)
  232. microcode in verilog?
  233. Synchronizing four phase-offset clock domains
  234. Setup time path on V4 SX w/ IDELAY
  235. small, free simple state machine processor suggestions?
  236. about XAPP028
  237. Two newbie Chipscope questions
  238. four phase clock using DCM with xilinx FPGA
  239. Digital Filter and external PLL (VCO)
  240. Constraining Multiple clock design
  241. Registered?
  242. Verifying a Bidirectional Data Bus
  243. edif format
  244. EDIF format
  245. EDIF format
  246. benchmarks for vhdl
  247. ISE 9.1i and partial reconfiguration
  248. PowerPC_DDR_controller
  249. How to ensure Select signal arrives after Input signals changed
  250. How to install xilinx ise8.2 in Madriva linux