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  1. WTF? - Spartan-3E starter kit with no printed board manual?
  2. Xilinx SRL's and sync flip flops
  3. sum of array
  4. Modelsim-SDF-Vital
  5. Modelsim - SDF incompatibility
  6. Can you change the default settings for XST when running platgen?
  7. help !something wrong with Adaptive Filter (vhdl code)
  8. faq
  9. 3.3V tolerant Virtex-4 JTAG Configuration
  10. Heatsink on FPGA?
  11. /* synopsys enum state_code */ on XST???
  12. PAL
  13. Initialization of arrays in Verilog
  14. ISE synthesis works, XPS does not resolve symbol?
  15. Estimating number of FPGAs needed for an application
  16. Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
  17. EDK & custom board definitions
  18. Dual edge detection
  19. Need help bringing up PCIe at the physical layer.
  20. Re: Xilinx: Case Statements
  21. Comunicate FPGA to Ethernet
  22. Xilinx: Case Statements
  23. Heritage Data books!
  24. Design report does not show BRAM usage
  25. Are FPGAs go enough for clock dstribution
  26. ddr sdram controller
  27. Addressing scheme in Block RAM
  28. Last Call for Papers (extended): The2007 International Conference of Computer Science and Engineering (ICCSE 2007)
  29. Any Western NC VHDL Designers?
  30. XST 9.1 hates VHDL character types
  31. Virtex 4 FX12 - where are the EMACs and PPC core located?
  32. Europe to Test 1000s Chemicals on Millions of Animals
  33. Xilin X-Fest Lunacy
  34. RLOC not working correctly in ISE 8.2 and 9.1?
  35. data2mem crash
  36. Xilinx Spartan DCM jitter spectrum
  37. Load V4 bitstream encryption key with XSVF
  38. Driving PLL from general I/O in Altera Cyclone
  39. XILINX ISE PAR error: CLK0_BUFG_INST is not placed
  40. Xilinx CoreGen fifo - ngdbuild error
  41. How best do I implement routing boxes in RTL?
  42. CAN vhdl code document
  43. odd warning in Xilinx ISE webpack
  44. Avnet Virtex-4 FX12 mini module
  45. FPGA Vs ASIC design and implementation
  46. using XIlinx impact in batch mode to generate EEPROM files
  47. Introducing picosecond delay between two output signals
  48. DFF with clock and async-preset tied together
  49. Spartan3AN - Roadmap
  50. DCI termination mismatch error reported in ise91
  51. Query regarding Project.Plz help very urgent
  52. Where do I find CMOS image sensors and lenses?
  53. No Clock in ChipScope Pro Analyzer
  54. Last Call for Papers (extended): The 2007 International Conference of Computational Intelligence and Intelligent Systems (ICCIIS 2007)
  55. Routing problem of DCM
  56. ISE & EDK on 64 bits linux machines - install story ;)
  57. Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
  58. Xilinx Ise 6.3i
  59. A Very good VLSI Chip design website
  60. VHDL and Latch
  61. Multiple devices within one ISE project
  62. Xilinx: it's about time!
  63. EDK 9.1 when?
  64. Ise foundation and Ise Webpack
  65. Nios II Multiprocessor Collection run in command line
  66. LCD code
  67. is bluespec pupolar in industry?
  68. Ideas for Masters Project.
  69. Integrate custom cores within Core Generator
  70. Large power planes vs. power islands vs. slits for decoupling
  71. Call for papers on Hardware Architectures for Genetic, Neural and Fuzzy Systems
  72. EDK 8.1i : add port for component
  73. regarding power and timing
  74. CUDD
  75. Boot uClinux from RAM without flash
  76. Multiplication operation
  77. V.34 Modem IP core
  78. New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
  79. DRP of the Virtex 5 PLL
  80. Sources (products) for Cannibalizing FPGAs, PLDs, etc.
  81. help read a pixel for picture
  82. Instance Name Being Removed?
  83. XST ucf timespec
  84. OPB-to-PLB bridge
  85. How to connect an IP to OPB bus??
  86. (( صــــور )) إيراني يفعل الفاحشة بالأطفال .. أنظـرو ما كان جزاء فعلته
  87. Virtex-5 are available from distribution
  88. What is the running frequency for a typical FPGA application using Virtex 5
  89. Help with Partial Reconfiguration on Spartan3
  90. apologia
  91. suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
  92. xilinx block ram synthesis
  93. looking for the source VHDL for Jpeg 2000
  94. Xilinx ISE Webpack 9.1 RTL schematic viewer problem
  95. Bypass caps, X2Y and 'puddles'.
  96. XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"
  97. google tech talks : "General Purpose, Low Power Supercomputing Using Reconfiguration"
  98. what about dma scatter /gather support in xilinx edk ipif ?
  99. Regional Clock Network and Large Designs
  100. Where can i get free CAN VHDL core
  101. what does a 'blank check' do exactly
  102. Altera Byte Blaster Cable on Linux
  103. Xilinx USB flatform cable length mistery ?
  104. Can write, can't read with OPB_SPI 1.00e
  105. SCons build tool as an alternative to makefiles
  106. Virtex 4 FX Sonet Alignment
  107. PCI-E TS1s
  108. How to implement pipeline in this case?
  109. How to implement pipeline in this case?
  110. How to implement pipeline in this case?
  111. Spartan MicroBlaze
  112. [Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
  113. Altera PowerPlay Power estimation
  114. MI5 Persecution: Troubling Censorship Issues 20/8/95 (3000)
  115. MI5 Persecution: Stand up for Free Speech 14/8/95 (345)
  116. ISE:Simulation
  117. How can we know how many BRAM are used?
  118. Handel-C, multiple clock domains, and PAL library
  119. Xilinx and archive of Teaching Materials
  120. Modelsim (errno = ENOSPC) error
  121. $recovery
  122. spartan 3E USB port... use for i/o instead of programming
  123. Verilog Programmer / FPGA Analyst
  124. Call for Papers with Extended Deadline: 2007 International Conference on Wireless Networks (ICWN'07), June 25-28, 2007, USA
  125. Call for Papers with Extended Deadline: 2007 International Conference on Embedded Systems and Applications (ESA'07), June 25-28, 2007, USA
  126. Redundancy
  127. OFFSET and Data Clock Skew?
  128. Spartan-3AN
  129. Virtex 4
  130. Spartan-3AN
  131. ML501 Platform Flash Configuration
  132. Virtex 4, how do I generate 100khz clock
  133. Xilinx platform cable USB API?
  134. XC3S400 and XC3S500E in PQ208
  135. Xilinx ISE webpack in Ubuntu?
  136. Edge vs Level triggering
  137. OPB BRAM not detected in EDK
  138. Bluetooth standard in software defined radio
  139. Making a 32KB BRAM block, virtex-4
  140. Making a 32KB BRAM block, virtex-4
  141. Call for Papers with Extended Deadline: 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'07), June 25-28, 2007, USA
  142. Xilinx Platform cable USB and impact on linux without windrvr
  143. MIG 1.6 on ISE9.1i
  144. How to specify ISE INST constraint with GENERATE statements?
  145. Interfacing to 10Gig ethernet with Xilinx FPGAs
  146. Call for Papers with Extended Deadline: 2007 International Conference on Grid Computing and Applications (GCA'07), June 25-28, 2007, USA
  147. Call for Papers with Extended Deadline: 2007 International Conference on Computer Design (CDES'07), June 25-28, 2007, USA
  148. Small FPGA Dev Board with Ethernet
  149. SystemVerilog?
  150. help for video compression
  151. Help for video compression
  152. demande aide
  153. demande aide
  154. Not power of two BRAM size problem
  155. Chipscope with Spartan 3E Starter Kit
  156. Call for Papers Reminder: The World Congress on Engineering WCE 2007
  157. Need help to buy first FPGA board!
  158. Need heep to buy first FPGA board!
  159. Structured ASIC players
  160. internal DCM
  161. 2x technique
  162. MicroBlaze and OPB block ram interface controller run at different frequency
  163. MicroBlaze and OPB block ram interface controller run at different frequency
  164. porting virtex2-pro into virtex4. Performance!!
  165. VHDL code for Generating registers
  166. Using Xilinx DCM FX output without DLL
  167. Determine error in asynchronous signal
  168. Call For Papers (Extended Deadline): WORLDCOMP'07 (June 25-28, 2007, Las Vegas, USA): computer science, computer eng., and applied computing conferences
  169. Can someone give me some pointers on using ibis models?
  170. OPB IPIF: write to DIER causing bus timeout
  171. how to use STD_LOGIC_VECTOR2
  172. up down lfsr
  173. nets vs. pads ; constraints question
  174. Cyclone II "altsyncram" timing constraints?
  175. Extended CFP for CIC 2007: (submission date extended to March 9, 2007)
  176. newbie question
  177. RTOS?
  178. Spartan-3E Sample Packs
  179. Looking for a superscalar simulator
  180. PETALINUX AUTO-BOOT
  181. Selecting device in Project Properties : no XC2V1000?
  182. can I convert DPRAM to SPRAM?
  183. Xilinx ML402 Virtex-4 Eval kit - I2C Bus
  184. Managing input clock of 20MHz at input of DCM
  185. configuring in slave serial mode with serial platform PROM
  186. How to get the area/time results without IO mapping
  187. Xilinx MIG DDR2 Documentation
  188. MIG 1.6 on ISE-9.1i-SP1
  189. ROC PORT
  190. ROC PORT
  191. MPD Files
  192. low cost xilinx prom burner?
  193. ACTEL ProAsic Plus
  194. Need help with VHDL simulation with SPW in Linux
  195. System Requirement to run V4Lx200,v5lx330
  196. Testing FPGA
  197. best way to get 4xclk
  198. need help on our thesis proposal in our school.
  199. Theora vs. M-JPEG2000
  200. Nexys from Digilent... aka, binge hacking
  201. Xilinx ISE WebPack Simulation Problem
  202. LUT based virtex multiplier
  203. Where to start???
  204. Does Xilinx XST synthesize combinational divider?
  205. Verilog: Simulating Transport Delays on Bidirectional Tristate Lines
  206. Has anyone gotten the GSRD to run from Ace CF?
  207. Lattice / M-LVDS
  208. ModelSim EDK Sim Problem
  209. Call for Papers Reminder: The2007 International Conference of Systems Biology and Bioengineering (ICSBB 2007)
  210. using shared vhdl code in customer ipif block
  211. FFT IP ALTERA FORMAT
  212. EDK Simulation on NCSIM
  213. Can't be too thin or too rich or have too many ground pads
  214. ML403 FPGA and CPLD
  215. Can't get the ACE to run software apps on the ML403
  216. ppc405_1 and LED in EDK
  217. Spartan 3 Output Driver Issue
  218. Xilinx Platform Studio adding Xilinx coreGen IP
  219. MGT free design papers.
  220. Need fair opinions on choosing either Altera or Xilinx as main FPGA source
  221. wintel CPU reads across the PCI Express bus
  222. Minimum Speed of DDR / DDR2 SDRAM w/o DLL
  223. OPB BRAM not bein detected
  224. picoblaze assembler : kcpsm3.exe and wine/linux
  225. CoreABC on M7A3PE600
  226. Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
  227. MGT RXRECCLK using 3 Global Clocks!
  228. regarding VREF and VCCO and GCLK in virtex 2 pro fpga
  229. IP to OPB FIFO
  230. Is there any version of Aurora protocol which works with LVDS instead of MGTs?
  231. Last Call for Papers: 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'07), June 25-28, 2007, USA
  232. Need FPGA recommendation
  233. Last Call for Papers: 2007 International Conference on Grid Computing and Applications (GCA'07), June 25-28, 2007, USA
  234. Last Call for Papers: 2007 International Conference on Computer Design (CDES'07), June 25-28, 2007, USA
  235. audio low pass filtering in FPGA
  236. SelectMAP Configuration and Readback
  237. Typical clock frequencies of FPGA designs
  238. Unable to load FPGA image from the prom
  239. How to develop STM-16 framer in FPGA
  240. Which is your favorite FPGA language?
  241. Understanding something in a bsdl file
  242. MPMC2 for Virtex-5 when?
  243. Master IPIF interface
  244. PETALINUX-COPY-AUTOCONFIG ERROR
  245. Building Coaxial transmission line on PCB?
  246. Picobalze in the FPGA
  247. Problem with floating inputs on LVDS ports
  248. Weird problem with WP 9.1sp1 and XC95144XL
  249. Last Call for Papers: 2007 International Conference on Wireless Networks (ICWN'07)
  250. FPGA configuration direct from PLX