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  1. ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
  2. lwIP, temac, and DMA
  3. POC at Element CXI
  4. has anyone used mathstar field programmable object arrays?
  5. Wanted: XUP Virtex II Pro DDR-controller
  6. ERROR: ::xilinx::Dpm::TOE::execInterrupt doesn't know what to do.
  7. Help!! FIR Polyphase second - order interpolator
  8. FIFO newbie question
  9. Query in Parallel CRC(urgent)
  10. Please HELP: timing problems on Virtex-4FX
  11. Xilinx WebCase support
  12. CPLD + µC with reasonably-priced tools?
  13. Flip Flop problem (asynchronous or synchronous???? )
  14. Flip Flop problem (asynchronous or synchronous???? )
  15. Problème de bascues (asynchrone ou synchrone?)
  16. EDK 8.2 MicroBlaze Tutorial
  17. Available: Detailed RISC CPU IP Core Design Documentation
  18. System Generator pcore I/O performance results
  19. Ross Freeman - inventor of the FPGA
  20. JTAG Tap Master (was: TI Tap Controller std8980)
  21. website for chip designers
  22. SetJmp/LongJmp for Microblaze
  23. Newbie with bus width mismatch problem. Quartus II
  24. VIrtex-4 FIFO16
  25. C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")")
  26. Why I cannot use the XAUI core(generated by xilinx)
  27. is there any opensource alternatives to platformstudio and microblaze development?
  28. File open, read and write in Xilinx EDK 7.1
  29. record type port in vhdl and simulation in ISE
  30. Modelsim Low and High violations
  31. Word sync in Cypress FX2 fifos /w 8 bit bus
  32. MGT Clocking
  33. Looking for Xilinx fpga board that works in Linux and has Ethernet card
  34. ByteBlaster Parallel Driver for Linux > 2.6.13
  35. Measuring the period of a signal
  36. Clocking data into a shift register on positive AND negative edges
  37. How do I use the Xilinx USB download cable for testing?
  38. query
  39. Xilinx ISE constanly asking to regenerate a core file.
  40. raggedstone + xc3sprog?
  41. A new way to define systems of systems?
  42. ispLever FTP Download
  43. can anyone give me a reference price of the following Xilinx boards?
  44. How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
  45. XUP virtex-II pro
  46. Icarus Verilog
  47. Nios2: elf2hex settings for epcs bootloader
  48. Nios2: elf2hex settings for epcs bootloader
  49. virtex 4vfx12 evaluation kit schematics
  50. Memory Interface Recommendation for ML410 Design
  51. Transition from ASIC to FPGA
  52. PCI FPGA Dev Board Suggestions
  53. Hundreds of solutions manuals in Pdf format
  54. what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
  55. suitability of systolic architecture on FPGA
  56. having a state machine in a datapath element a bad design practice?
  57. Gray code in asynchronous FIFO design
  58. Re: TI Tap Controller std8980
  59. Interfacing the DAC0808 to FPGA
  60. Digital Receiver chip suggestion
  61. TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
  62. fifo occupancy bigger than fifo size?
  63. high number of multipliers / low cost
  64. Can I boot PowerPC without JTAG?
  65. Problem with PHY clocks on Spartan 3E Starter Kit
  66. Conceptos about VCCINT,VCCAUX,etc
  67. MIG under Linux
  68. Xilinx: WARNING:PhysDesignRules:372 (What the heck?)
  69. Looking for Memory Recommendation for Spartan 3E 1200
  70. Boot PowerPC on VirtexIIPro
  71. RFC: VHDL testbench enhancements
  72. QUIP write_verilog.c
  73. Implementing a communication protocol for data transfer over TCP on an FPGA
  74. re-assemble bootloader for NIOS Processor
  75. Implement IIR Filter on FPGA
  76. ISE 9.1i SP3 simulator problems on Linux
  77. X_OBUF and other error messages with ModelSim
  78. Does the XC3S250E-VQ100 exist?
  79. Dynamic Reconfig
  80. MGT Digital Receiver Oversampling
  81. Standard PCI Xilinx board with Ethernet port
  82. verilog genvar, and 2D array access
  83. SVF Player
  84. EDK 9.1i installation
  85. Dear Xilinx
  86. how to use and calculate prom checksum in prm file.
  87. broken mb-gcc -O2 ?
  88. DCM_STANDBY macro in Virtex-4
  89. Question about initializing the ram value in test bench
  90. Thomas & Moorby Verilog Reference: $41
  91. How much time margin should I give to a SDRAM interface via FPGA?
  92. Spartan-3A XC3S1400A development board?
  93. Altera ASMI_PARALLEL megafunction (EPCS4/CycloneII)
  94. microblaze bootloader
  95. ISE on Fedora?
  96. Config PROM for Spartan II
  97. Static RAM implementation with VHDL
  98. Static RAM implementation with VHDL
  99. Help with a face recognition system
  100. Sysgen compilation target
  101. Another simple DCM question
  102. ModelSim VHDL Pragmas
  103. EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07
  104. Xilkernel-EDK8.2
  105. Xilkernel-EDK8.2
  106. Xilkernel-EDK8.2
  107. xilinx ise/edk/modelsim - what does compilation really do?
  108. Complex Baseband
  109. "undeclared here" error and undesired file persistance in Xilinx Platform Studio
  110. RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
  111. Webpack 9.1 Service Pack 3
  112. Regarding connecting two Ethernet Mac Phy
  113. We need avnet fx12 mini module URGENTLY!
  114. Some errors i dont know in XMD
  115. Watershed Transform
  116. suggestion for choosing the right FPGA for gigabit transciever
  117. Need help with sequential fault simulation in Tetramax!!!
  118. Problems with Xilinx Parallel III Cable
  119. How is it possible to design a convolutional interleaver with sequential memory writes?
  120. Compiling simulation libraries of EDK 8.1.02i under Linux
  121. LC8
  122. Confuse on Spartan speed
  123. FPGA board with multiple Ethernet connections (Gigabit Ethernet)
  124. is edk 8.1 availabe for download
  125. ANNC: Tips for FPGA Timing Closure Webcast
  126. What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
  127. longest webcase record
  128. (Xilinx) OPB watchdog timer fails to release RESET
  129. Help with Xilinx Parallel Cable IV.
  130. Lattice "Open IP" license is GPL-compatible?
  131. Re: EDK : Import Custom Peripheral
  132. PCI-Express drivers with Xilinx FPGA?
  133. CycloneII altlvds_rx
  134. Open-source CPU-core for standard-cell ASIC?
  135. Where is MIG 1.7???
  136. FPGA board with multiple Ethernet connections (Gigabit Ethernet)
  137. Post PAR simulation for RAM Block implementations
  138. Post PAR simulation for RAM Block implementations
  139. No results show up after "dow" and "con" in hypertrm
  140. Spartan 3E Not enough block ram.
  141. A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
  142. RISC implementation questions
  143. Minimal pins for JTAG configuration
  144. how to read a sequence of video
  145. Quartus warning messages reagarding timming and latchs
  146. Delta Sigma A/D's integrated in FPGA's
  147. Small memories in Cyclone
  148. Where is Open Source for FPGA development?
  149. help needed
  150. Tool to convert ISE project into makefile? (for Linux)
  151. Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??
  152. convertion real to std_logic_vector
  153. shift register with distributed ram
  154. shift register with distributed ram
  155. Solaris 10
  156. Amphion IP MPEG2 Video DecoderCores
  157. iMPACT:CRC Error bit is NOT 0
  158. VDC needs help with ESL/EDA Survey
  159. EDK and Custom Peripheral: error occur when generating bitstream
  160. Custom IP ports to be used as GPIOs
  161. Flash memmory model
  162. problem while using if or case statements
  163. IEEE 802.3 Ethernet MAC implemetation in FPGA
  164. URGENT HELP NEEDED: LVDS
  165. multiple clock domain issues
  166. Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
  167. Parallel Cable IV in Spartan 3E???
  168. Matrix inversion in FPGA
  169. CRC check error
  170. Digital AM/FM Receiver - Systemic Question
  171. Looking for resources on timing analysis
  172. Manual LUT - AND function mapping problem
  173. how to shift mutiple bytes in an array in one clock cycle?
  174. gated clock
  175. LZW compression and decompression in vhdl
  176. CPLD erase??
  177. How to generate STAPL with "pulse PROG" in Impact?
  178. Data width in Block ram
  179. How to make use of two processors with Xilinx ISE (on Linux)
  180. Austin the Altera Mole
  181. how to make a matlab simulink wave into mif or hex form.
  182. Why is Xilinx's WebPACK so inferior?
  183. Virtex-II block RAM problem
  184. Zero-Valued Data Out of Chipscope ILA?
  185. 1.8V config proms for Cyclone 2s
  186. softcore CPU tools
  187. FF's are inffered instead of distributed RAM
  188. Using xilkernel with C++
  189. FPGA with 5V and PLCC package
  190. Automatically adding pcore from XBD (Xilinx Board Definition) file?
  191. prog_b held low?
  192. timing in xilinx fpga
  193. create test bench of video
  194. Wanted: container classes for reconfigurable computing
  195. Xilinx ISE Inferred block rams
  196. Sparten 3E clock generator
  197. ModelSim PE exit code 211
  198. Altera introduces Cyclone III devices, ships 65nm
  199. a project work
  200. alliance tooset on Linux
  201. direct access on opb_emc
  202. QuickSilver's ACM architecture
  203. IOSTANDARD default value in Xilinx UCF-Files?
  204. Jam STAPL Player extensions
  205. ADC capture with FPGA Spartan3 in Verilg
  206. FPGA vs. GPP anyone?
  207. CFP : FPL 2007 (Submission deadline extended to 25th of March)
  208. how to transform Arun's LDPC code to max-product (Min-sum)?
  209. How to find pcore directory from within EDK TCL script?
  210. Eval board advice
  211. XPower crashes....
  212. Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
  213. Xilinx XST 9.1, Verilog 2-D arrays, always @*
  214. Systemverilog preprocessor allow "..."?
  215. What official function should I call to genertate a sum of products in VHDL
  216. Xilinx ISE support for dual/quad core CPUs?
  217. Virtex5 LXT and synthesis..
  218. Xilinx Synthesis Attribute usage
  219. dual PowerPC booting
  220. MXE compilation error
  221. XILINX ISE: How to define a Internal clock and use it in OFFSET command?
  222. chipscope
  223. init of FPGA's Block-RAMs.
  224. How to generate sgmii interface?
  225. old Quartus project files
  226. Problem with XESS XSA 3S1000!
  227. How to use the DDR SDRAM instead of Block RAM?
  228. DCM Autoconfiguration??
  229. XIlinx 9.2 'partition' mode problem - s/w dies....
  230. ChipScope problem: "Waiting for core to be armed".
  231. Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)
  232. Fpga sdr boards / kits
  233. Xilinx Xplorer misfunction
  234. doubt in verilog coding
  235. DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY
  236. .bit file to VHDL/verilog source code
  237. .bit file to VHDL/verilog source code
  238. Welcome to X-Fest 2007
  239. SEC:U Problem getting rid of bit latch errors
  240. SEC:U Problem with bit latch warnings
  241. Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
  242. Clearing fpga internal memory...
  243. Xilinx Netlist
  244. Xilinx FPGA, OFFSET OUT AFTER
  245. interface ad9229 with altera stratix II
  246. Programming XCF from MicroBlaze over JTAG???
  247. ANNC: Clock Network Implementation Webcast
  248. qemu+ghdl or uml+ghdl hardware-software cosimulation?
  249. PCI - Express
  250. using system ACE for generic app data storage - file system intelligencerequired?