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  1. MGT Clock
  2. Power PC heap initialisation on Reset
  3. ISE and total equivalent gate count
  4. Lattice XP2 finally announced
  5. any experiences concerning xup and digilent inc.?
  6. CFP: International Conference on Modeling, Simulation and Control (ICMSC 2007)
  7. TBUF and modular design flow on spartan
  8. Problem with System ACE
  9. Create and Import Peripheral in EDK
  10. Synchronization of instruction with clock
  11. Altera Serial Flash Loader (SFL) question
  12. Microcontrollers have a better predictable time behaviour than FPGAs
  13. Raggedstone1 Brackets
  14. ngdbuild error : multiple drivers and driving non buffer primitives
  15. FIFO : Synchronous WRITE, Asynchronous READ ?
  16. Xilinx OPB External Memory Controller
  17. LocalLink TEMAC Data Corruption
  18. How to execute application code out of external memory using EDK?
  19. What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
  20. Calls for Papers: International Conference on Intelligent Automation and Robotics (ICIAR 2007)
  21. Weekend pop quiz
  22. Tristate ipcore problem with XPS
  23. xilinx parallel cable troubles
  24. Modular Design Example
  25. How to guarantee the same relative placement and routing in ISE?
  26. ML402 development board
  27. Bootloader in BRAM to run a program loaded in the DDR
  28. Cyclone 3 Starter Board connector?
  29. CoreGen Issues ??
  30. ise9.1 : partitions with edif flow
  31. using ICAP with the ML310
  32. Regarding multiple write problem in opencores pci bridge
  33. Virtex-4 troubles after configuration
  34. Xilinx MIG and verifying UCF files
  35. Some doubts in the FPGA design flow in the ISE
  36. Can anyone explain the details of the FPGA design flow in ISE
  37. Can anyone explain the details of the FPGA design flow in ISE
  38. Actel Cortex M1, any info on license fee?
  39. s3 starterkit problem
  40. After PAR simulation, should I assume that it will work on FPGA board?
  41. Can't get AREA_GROUP to work
  42. FIR ON FPGA
  43. Cyclone 3 Starter Board Question
  44. Can't get AREA_GROUP to work
  45. Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling
  46. Spartan 3E Starter Kit and EDK 8.2
  47. Chain of LUTs is being removed during par
  48. Ise Flow with PowerPC
  49. data compression algorithms on FPGA
  50. Call for Papers: International Conference on Circuits and Systems ICCS 2007
  51. 180 differential inputs each 800Mbps using V5
  52. Building Gradually Expertise on VHDL/Verilog Design
  53. ANNC: Secure FPGA Configuration Over Ethernet Webcast
  54. Virtex4 Configuration Problem
  55. Virtex4 Configuration Problem
  56. XS40 Download Cable
  57. Spartan-3E DIG-3E1600 Development Board Kit
  58. Nexys by Digilen xbd file
  59. Xilinx CIC core in Spartan 3?
  60. Help: Best use of DCM in Spartan-3A?
  61. what is register packing?
  62. Inverse of a matrix
  63. FIR Filter ON FPGA
  64. spartan-iie
  65. Xilinx Seminars in Wiesbaden, Berlin, Hannover
  66. ISE/EDK Kubuntu linux installation issues
  67. Xilinx Coregen 2.3 problem
  68. Linux device driver for FPGA Xilinx Virtex-4
  69. Linux device driver for FPGA Xilinx Virtex-4
  70. Microchip ICD on FPGA
  71. How to calculate IFFT based on FFT result?
  72. PacoBlaze 2.2
  73. comp.arch.fpga :How to implement a 128-bit input CRC module inV5
  74. Rodney Smith, long term Altera CEO, dies in accident
  75. Quartus-II 7.1 Systemverilog interface?
  76. JTAG fundamentals question
  77. MPMC2 + flash bootloader problem
  78. Is this the correct way to design FPGA to DRAM interface?
  79. 3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007
  80. Proper word for total delay?
  81. accesing JTAG ports on GPIOs
  82. Atmel FPSLIC users out there?
  83. SignalTap Analyzer...
  84. Quartus-II 7.1 Systemverilog support define `` ?
  85. Best way of moving paralell bits of data from over clock domains?
  86. Looking for experiences with SUZAKU SZ010/SZ030
  87. 6502 FPGA core
  88. Spartan3 LVCMOS33 Slew rate
  89. EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
  90. Interfacing EDK application code with Specific BRAMs on FPGA
  91. low speed communication
  92. PC to JTAG
  93. ISE 9.1 and ModelSim XE III/Starter 6.2c: Distributed memory behaviorial simulation
  94. IOSTANDARD user constrain
  95. ML505 : beginners problems
  96. Has anyone used Sundance Boards?.
  97. HI EVERYBODY PLEASE.... HELP REGARDING DDR 2 CONTROLLER
  98. Went from Xilinx to Altera: Cyclone-II and I/O pullup?
  99. Testbenches in C driving ISE simulator?
  100. VGA signal through breadboard?
  101. How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
  102. Docs on s/w interfacing EDK based design
  103. How to code a bidirectional databus?
  104. Actel timing constraints
  105. ModelSim Memory Content import from Intel Hex
  106. Dual Core or Quad Core when running Quartus 7.1
  107. Use BRAM as ROM (Xilinx)
  108. Quartus 7.1 segv on recent Linux distributions
  109. Xilinx 8.2 : Multippass P&R
  110. Ddr sdram feedback pin
  111. How can i command bit Inputs in an FPGA board?
  112. LVDS termination scheme to nonstandard ribbon cable
  113. 6502 and CPU licences in general
  114. Error while generating Libraries and BSPs.
  115. SATA OOB detection with Virtex5
  116. fit_timer: trouble connecting interrupt
  117. Custom Memory Initialization
  118. Altera Cyclone II - used in 100USD Laptop
  119. problem while reading from DDR 2 memory
  120. clarification: clock doubling in Spartan 3
  121. Re: Project Navigator / Verilog / +define
  122. Project Navigator / Verilog / +define
  123. Binary to BCD
  124. Project Navigator / Verilog / +define
  125. Re: How the synthesizer acutally works.
  126. Re: How the synthesizer acutally works.
  127. Xilinx ML405 / VxWorks 6.3 Bootloader
  128. DDR SDRAM in custom board
  129. Re: LVCMOSS33 I/O sink current
  130. Re: PLB behaviours strangely during burst transactions
  131. Re: PLB behaviours strangely during burst transactions
  132. How the synthesizer acutally works.
  133. Re: SelectIO banking rules
  134. Re: SelectIO banking rules
  135. M-RAM allocation in Stratix EPS125B672C6
  136. Design running on board but timing are not met
  137. LVCMOSS33 I/O sink current
  138. JTAG FPGA Debugging
  139. ISE Service pack
  140. how 33-bit BRAM?
  141. ISE Service pack
  142. System-synchronous interface clocking between FPGA's
  143. "black_box"-ing of components in toplevel
  144. Problems to simulate (behavioural) in XPS
  145. Problem with DDR2 controller
  146. PLB behaviours strangely during burst transactions
  147. PLB behaviors strangely during burst transactions
  148. using FPGA JTAG as GPIO
  149. DDR Controller Blue
  150. Xilinx doesn't detect setup/hold violations on synchronous reset
  151. Atmel release Metal Programmable Cell Fabric uC ARM9
  152. How to copy hex data from Quartus vwf file to text?
  153. ModelSim version upgrade problem from 6.1c to 6.2c
  154. Does FPGA need CPU for processing a packet/frame
  155. Does FPGA need CPU for processing a packet/frame
  156. Does FPGA need CPU for processing a packet/frame
  157. SelectIO banking rules
  158. Error in NGDBuild
  159. Call For Participation: WORLDCOMP'07: joint conferences in CS, CE, and applied computing, June 25-28, 2007, Las Vegas
  160. Cyclone FPGAs in Switzerland
  161. Timing not met but working on board
  162. Filtering the FPGA reset signal
  163. UART Receiver Parity Check
  164. Support you the best free forum forever !
  165. AccelDSP Systemgenerator ML403
  166. Signal Assignment bugs in Quartus-II ... AGAIN!
  167. Signal Assignment bugs in Quartus-II ... AGAIN!
  168. external clock frequency doubles
  169. releasing some FPGA tools-ip as open-source
  170. EDK 8.1i to EDK 9.1i UCF file errors
  171. How do I constraint multiple clock cycle in Altera?
  172. How to insert tab in Write() function in VHDL
  173. Quartus 7.1 Simulations
  174. I need advice
  175. Single Chip MSX computer full schematic and VHDL sources
  176. Precision RTL and DesignWare libraries
  177. Xilinx Timing Constraint Questions
  178. How to port simulink design to FPGA?
  179. Visio logic symbols
  180. Proper/recommended method for driving clock out from FPGA
  181. SystemC and TLM
  182. video soltion provider
  183. Mobile DDR vs DDR2
  184. Re: Fortran to matlab infuriating problem
  185. FPGA and LEGO Mindstroms
  186. Unusual question about generic port use (optional ports??)
  187. Semaphores in xilkernel?
  188. DDR 2 Memory controller own implementattion
  189. VHDL newbie: building sequential circuits with basic gates
  190. can JTAG port of CPLD gets damaged?
  191. too brief documentation?
  192. Avnet Virtex-4 LX25 Evaluation Kit
  193. Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
  194. Cyclone II can't enter in configuration mode with EPCS1.
  195. Cyclone II can't enter configuration mode with EPCS1 active serial.
  196. seeking insights for potential reconfigurable computing application platforms
  197. Mutiple MAC on OPB Bus
  198. CML output swing for V5
  199. NIOS2 GNU tools under Windows Vista
  200. Unable to scan JTAG chain
  201. how to delay a signal in virtex FPGA
  202. clock wide pulse transfer b/w clock domains
  203. Global ressource problem
  204. Mind Control and Directed Energy Weapons
  205. SERDES question (Lattice ispHSI)
  206. Power Consumption near Timing Failure Point
  207. Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
  208. Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
  209. Designer
  210. LF VHDL to FSM bubble diagram translator
  211. ise project navigator can't dereference edk pcores from XilinxProcessorIPLib
  212. Using dynamic reconfiguration ports of DCMs on Virtex 4
  213. Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory
  214. debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL
  215. How low DDR2 Clock Frequency can be? To make it work on FPGA.
  216. Xilinx ISE 9.1 Simulator does not work with glibc 2.5
  217. coregen -> simulation error in modelsim
  218. Xilinx EDK: Slow OPB write speeds
  219. reading IDCODE from parallel bus?
  220. bus macros for partial reconfiguration of virtex2pro?
  221. Timing constraint question
  222. Lockup with Xilinx mch_opb_ddr
  223. does SRL exist in non-xilinx FPGAs?
  224. Anyone using the TimingAnalyzer
  225. Camera Control
  226. Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
  227. How to Ask a Question
  228. Digital gain and offset correction
  229. Xilinx Webpack 9.1i.03 Verilog synthesis bug?
  230. Xilinx Webpack 9.1i.03 Verilog synthesis bug?
  231. downto usage in EDK
  232. plb_tft_cntlr_ref in XUP
  233. PowerPC_GPIO
  234. PowerPC_DDR
  235. Power Consumption Estimation for PCI card, any advice?
  236. how to choose the perfect fpga support
  237. V4FX PPC ICU data transfer timeout?
  238. Uart problem, xapp223 + Spartan3A
  239. power consumption of integrated circuit in 0.13Ám CMOS technology
  240. xc3sprog and spartan 3e/3a
  241. NgdBuild:604 error
  242. V5 serial link
  243. JTAG_SIM_VIRTEX5
  244. Xilinx ISE Simulator 9.1.03i: A bunch of problems (Block Memory Gen.)
  245. ISE9.1: ERROR:Place:911
  246. Accessing SRAM on the Spartan-3 Starter Board
  247. Altera enters as second the low-cost multigigabit tranceiver FPGA scene!!
  248. Call for Papers: World Congress on Engineering and Computer Science WCECS 2007
  249. Craignell - Spartan-3E DIL Module
  250. Gain and Offset Correction