PDA

View Full Version : FPGA


Pages : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 [41] 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

  1. Alter RBF Compression
  2. ISE or EDK?
  3. microprocessor on fpga problems
  4. Building a Huffman codebook in VHDL
  5. Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
  6. DVB-T/H help me ?
  7. virtex-4 power consumption
  8. xilinx 3adsp starter kit : where are demo and reference designs ?
  9. Files produced by Quartus II compiler
  10. LEDs, buttons and LCD
  11. FPGA input level conversion
  12. mess around with supply voltage to cyclone III
  13. Wishbone Specification in Action
  14. Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"
  15. Fast Sampling of digital signals
  16. FPGA pin swapping utility
  17. VHDL trivia?
  18. Dynamic Reconfiguration books
  19. xilinx Edititons
  20. What to consider for source synchronous clocking?
  21. systemc thread processes are called with the same thread in windows
  22. difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
  23. FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
  24. Reason for LUT1_L buffer insertion in Synplify EDIFs?
  25. xil_printf and %u specifier
  26. Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files
  27. FPGA quiz 1&2, we have the answers and winners
  28. High level FPGA work flow: available tool?
  29. IPs in MHS file
  30. gold code - seed value
  31. ethernet phy or mac
  32. FPGA to FPGA Bus
  33. RTM ERROR:fail to get the remote thread list.
  34. Xilinx:is it possible to install Impact 9.1only?
  35. FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
  36. Xilinx FIFO Flag Question
  37. Xilinx timing constraints incorrect?
  38. DWARF2 in MicroBlaze?
  39. FPGA quiz: what can be wrong
  40. profiling in modelsim
  41. FIFO depth
  42. Altera devices connecting to DDR memory.
  43. Call for Papers: IAENG International Conference on Software Engineering (ICSE 2008)
  44. Watch NFL Games Online
  45. where to download latest systemc libararies?
  46. MIG for Linux?
  47. Newbie,the simplest way to program an FPGA at home?
  48. Quartus II Web Edition License - SOPC Builder generation?
  49. Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?
  50. NgdBuild:455 Multiple Drivers
  51. Graphical VHDL Viewer ?
  52. Xilinx OCM memory use limitations ?
  53. Quartus II 7.2 web edition - Linux or not?
  54. Xiinx ERROR:PhysDesignRules:10
  55. FPGA tools under VMware or Parallels on a Mac?
  56. Cyclone II SSTL-2 on-chip resistors
  57. HELP, how to time constraint part of a design?
  58. What happened to Confluence and HDCaml?
  59. Compiler Options
  60. Unrouted nets (Xilinx FPGA Editor)
  61. UK Supplier XILINX spartan 3 development board??
  62. Quartus-II 7.2 web-edition Systemverilog improvements
  63. Xcell Article on 1.2Gsamples/sec FFT
  64. Timing Constraint Question
  65. Legacy support of a Max 7000S
  66. DDR DIMM clock distribution
  67. 8B/10B Xilinx Paper
  68. code coverage in modesim se 6.1f
  69. Starting FPGA
  70. CY22393
  71. Need suggestion on FPGA kit
  72. Neural Coprocessor with Xilinx EDK
  73. Cyclone II - PLL differential output
  74. kicad or orcad virtex5 symbol
  75. code coverage in modelsim_se
  76. Free Background Check
  77. JTAG interconnect testing, prototypes
  78. FiberChannel SOF
  79. Opteron performance tuning (for Quartus / Linux)?
  80. Virtex 13?
  81. Computer Security Information (Free Articles and eBooks)
  82. How to do one hot state machine in verilog for Xilinx V5 using XST
  83. Daisy chaining FPGA with CPLDs
  84. Problem about ADV7181B debugging
  85. Best way to export XPS project to ISE?
  86. xup-v2p: Only USB 1.1
  87. JPEG-LS hardware implementation
  88. Optimized bitcounting on FPGA
  89. FFT core
  90. Companies that Manufacture Multi-FPGA Hardware
  91. XUPV2P serial connection through serial-to-usb cable
  92. Detecting if an error happened in ModelSim
  93. Tcl - Xilinx - ISE - WindowsXP
  94. Partial/Incorrect configuration of FPGA from flash PROM.
  95. Basic VHDL Development kit
  96. Any better ways for interfacing fpga with dynamic memory?
  97. CFP: SCALABLE COMPUTING. Special Issue on High Performance Reconfigurable Computing (HPRC)
  98. Get unlimited visitors to your website
  99. Virtex4: ISERDES -> FIFO -> BlockRAM fails
  100. ALTERA Quartus 7.2 under MS Vista
  101. Call for Papers: The IAENG International Conference on Industrial Engineering (ICINDE 2008)
  102. Test and Measurements - Large FPGA
  103. Spartan3E DDR clock feedback
  104. Count Leading Zero (CLZ) possible by MicroBlaze??
  105. Error in simple code, plz help
  106. Xilinx ISE 'feature': forcing a DUT signal
  107. Synplicity and the Xilinx MAP Memory Monster
  108. Planning to switch to FPGA domain, any advice would be highly appreciated
  109. Walking 1's
  110. www.fpga-games.com website died?
  111. please help me for vhdl code of temprature controller
  112. XUPV2P from digilentinc
  113. [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
  114. Programming the ARM7 used to download our Xilinx FPGA
  115. 2 leg crystal on FPGA: Lattice vs Xilinx
  116. LVDS clock management
  117. FPGA NTSC signal with 2 resistors and PWM
  118. Check it out:Very good online resources,tons of cool men and beautiful women eager for lovers....:
  119. PowerPC Simulation
  120. Xilinx upgrade
  121. UCF Constraints: drive and slew
  122. FPDP to PCIe
  123. Bug in Synplify?
  124. Basic questions about the Nios II.
  125. Stratix GX
  126. Inferring wide adders comprising multiple DSP48s
  127. YARDstick custom processor design tool homepage updates
  128. Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
  129. XST corrupts my state machine. Only disabling FSM encoding helps
  130. Very basic clock questions.
  131. Logic minimization software with LUT6 support?
  132. Own soft-processor
  133. How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
  134. Never buy Altera!!!!
  135. Variable Phase Shifting for VirtexII DCM
  136. DRAM modules - RIMM, SODIMM,UDIMM..etc
  137. Check it out:Two best way to get friends worldwide
  138. Automotive Electronic Control
  139. partial reconfiguration, par error
  140. [ANN] FPGAOptim - Do you know where your slices are going...?
  141. BRAM bytewide write enable problem
  142. ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
  143. Check it out:#1 social network,download free,stock information,knowledge base,hot videos,hot games and hot tickets...
  144. Xilinx GTP based serial link
  145. Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation,and Optimization" ?
  146. FREE BACKGROUND CHECK
  147. CRC calculation of Virtex 4 bitstream
  148. Does Modelsim work under Windows Vista?
  149. Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
  150. Answer: maximum number of state machines in a current chip: > 500k
  151. DDR RAM timing contraints
  152. Configuring Impact on any version of linux
  153. baord for learning softcore processor
  154. Using PlanAhead for Partial Reconfiguration
  155. Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
  156. how interfacing of cpld and cpu done?
  157. hardware software codesign
  158. Comparing Adder synthesis techniques
  159. DMA scatter gather with PLB bus?
  160. Is it possible for two wires to share the same FPGA pin?
  161. proasic plus. actel
  162. Multi-cycle paths in VHDL libraries
  163. Gated Clock Problems
  164. Check it out:download free,stock information,knowledge base,hot videos,hot games and hot tickets...
  165. help! ACTEL PROASIC PLUS clock buffer
  166. FPGA history
  167. Recently Launched and So Powerfull
  168. ANNC: PCI Express and Ethernet Gaskets Webcasts
  169. Population Count circuit
  170. Verilog simple dual port memory with different input and output widths?
  171. Re: Symbolic names for pll derived clocks in SDC file? (quartus)
  172. Looking for fast AES cores with low latency
  173. Data-side BRAM
  174. Tristate bus on spartan FPGA
  175. Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
  176. Virtex-4 SELECT MAP configuration
  177. Directing data to DDR
  178. Altera / Lattice / Xilinx CPLDs ?
  179. ECP2/M und Serdes
  180. global clock on virtex5 question
  181. Unexplained behavior with DDR2 controller on Xilinx V5
  182. ASAP 2008: Preliminary Call for Papers
  183. Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  184. Get unlimited visitors to your website
  185. [ANNOUNCE] YARDstick - custom processor development toolset
  186. FPGA power optimize! Help
  187. sounds
  188. Get unlimited visitors to your website
  189. XAPP806 issues DCM Phase Shift
  190. Virtex II pro design question
  191. Beginner Advice (Languages, tools etc.)
  192. Learn About High-speed Serial Connectivity & FPGAs - for FREE
  193. add_file -verilog +define ..... filename.v
  194. post translate and post PAR problems with XST and Modelsim
  195. Spartan-3E Slave Serial Configuration
  196. Physical Design Contribution to FPGA/CPLD success
  197. Xilinx GSRD reference design and 3rd party synthesizer
  198. Is post-place and route simulation useful?
  199. Open-Source VHDL Synthesis for FPSLIC?
  200. Virtex-4 PCB design
  201. MicroBlaze Tutorial
  202. Problem with Microblaze max clocking
  203. genmcs.pl for a V4FX60 aka loading the cache from the prom on a multi processor device
  204. Virtex5 PLL for DDR2 interface
  205. Peripheral Trouble!
  206. Xilinx System Generator Error!
  207. overloading ' operators in VHDL
  208. Opening for Senior Level Design Test Engineer
  209. Urgent requirement for Sr.Engineer (Verification)
  210. Excellent Opening For ASIC Design Engineer !!!!!
  211. Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
  212. project in chennai
  213. XAPP851 fifo36 missing
  214. Ethernet Code Problem with Xilinx Spartan3E
  215. Altera + ARM Cortex-M1
  216. Re: precision errors. microblaze vs matlab single precision... huh?
  217. VHDL Design Pattern Book
  218. precision errors. microblaze vs matlab single precision... huh?
  219. Command line quartus_pgm very slow
  220. [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
  221. ML410 Board & 1GB DDR2 DIMM Problem
  222. Address sensitive process, Xilinx virtex2pro
  223. FPGA Archives
  224. Good VHDL reference?
  225. PCI byte enalbes in read cycles
  226. Stratix III Memory usage efficiency
  227. application about hardeware attributes
  228. microblaze toolchain compilation question
  229. hydraxc
  230. Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
  231. ACM SAC 08: DEADLINE EXTENSION (16 Sept, 2007)
  232. Uses of Gray code in digital design
  233. Question about Virtex-4 DCM
  234. 1/2 Convolutional Encoding of CNAV Data
  235. What is called carry chain structure in FPGA is called in IC?
  236. What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)
  237. VHDL Synthesis Error
  238. LVDS pin placing on CYCLON II problem
  239. Quick question for an Altera wizard
  240. Minimize power consumption
  241. Anyway to stop Altera Stratix II SignalTap data acquisition
  242. Help getting sdram running with EDK.
  243. Nios II -- Why does this error occur ?
  244. New keyword 'OIF' and its implications
  245. RE: FPGA/VHDL digital Design permanent role - Oxford
  246. SRAM on Cyclone Devices
  247. How to simple convert a hex or mif file from Altera to Xilinx coefile?
  248. [Nios II] How does the PIO Core generate a interrupt?
  249. Rocket IO clock
  250. DDR Simulation via MIG