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  1. Video Over RF - using bluetooth and Xilinx Video Starter Kit
  2. Over utilization of FPGA resources
  3. MULTICONF-08 Draft paper submission deadline is just few days fromnow
  4. Synthesis-Place-Route benchmark for i386-32bit
  5. Linux and the Digilent Basys ?
  6. Ballpark PLB frequency
  7. PC configuration for fastest compiles (synthesis, place and route,etc)
  8. distorted sine wave
  9. Virtex 4 package layout
  10. Spartan 3 configuration download error
  11. Reprogramming Proms,before the fpga boots from them (Avnetboard,Xilinx Proms)
  12. Microblaze 7.0 on V2pro?
  13. Rom Implementation in a CPLD
  14. Cyclone flash configuration data
  15. signal generation in VHDL on FPGA.... Check my code please
  16. i need fpga board with 10 Gig interface and pcie interface
  17. Call for Papers: World Congress on Engineering and Computer ScienceWCECS 2008
  18. i need ur help
  19. Erratic Behavior of Virtex 4 FPGA
  20. Virtex-4 input pad failures
  21. CFP: DTVCS 2008 - Design, Testing and Formal Verification Techniquesfor Integrated Circuits and Systems
  22. Virtex-5 User Guide "Lite"
  23. Is a FPGA the solution ?
  24. OT. Posting with Outlook Express?
  25. State machine outputs and tri-state
  26. HELP on PLL and DCM
  27. Xilinx GTP_DUAL: wizard or code ?
  28. When are FPGAs the right choice?
  29. setup time not met in Quartus
  30. floating point arithmetic in vhdl
  31. mb-g++ compilation error with EDK 8.2.02i
  32. Spartan 3A starter kit
  33. Newbie looking for guidance
  34. Redundant Ethernet connection
  35. Virtex4FX over-voltage
  36. XiRisc softcore processor
  37. Does PC-FPGA communication requires a driver?
  38. '1' or '0' when I/O pin is pulled up
  39. Vitrex5 JTAG capture and debug
  40. Partial reconfiguration reference design?
  41. Reed solomon IP core
  42. how to implement this...
  43. Xilinx ISE and XP home,possible?
  44. XC5VLX85-2FFG1153C
  45. ModelSim versus Active-HDL....redux
  46. Virtex5 DCM lower limit
  47. FSL version compatability with Microblaze version
  48. Unsigned to signed vector.
  49. Critical Path analysis
  50. RC340E board to sell
  51. FYI. Free Verilog cores from MIT.
  52. Call for Papers Reminder: The World Congress on Engineering WCE 2008
  53. Downloading codes to FPGA development Board
  54. microblaze firmware + UART handshaking blues
  55. loading unisim in modelsim problem while testin xilinx ipcore
  56. ANN CPLD add-on module for Nintendo DS game console
  57. My first verilog/cpld project
  58. multidimensional array
  59. Question to VHDL code fragment
  60. Timing Constraint not met
  61. Problem in assignment of pins in PACE
  62. Strange "Style guide" requirements...
  63. Looking for a development board
  64. How to get Map Repoprt after System Generator postmap estimation
  65. ANNOUNCE: Shanghai Many-Core Workshop
  66. impact bug or wrong interpretation of xsvf layout?
  67. Weired Distributed Memory behaviour
  68. I/O mode to use for USB ..?
  69. What does "Continuous Sample times are not allowed" mean in SysGen9.1?
  70. Marking Flase paths for Timing Ignore + Virtex 2 Pro support
  71. Prom alternatives for xilinx
  72. ML410 and documentation on ALi M1535D+
  73. Shutdown parts of core logic on FPGA
  74. beleive
  75. function/process to generate sine and cosine wave
  76. Virtex5 not for SONET or SDH
  77. Partial Reconfiguration of Virtex-5: ISE and EAPR?
  78. Single Top FPGA Tips
  79. Simple Memory Read problem, help appreciated
  80. Simulator error 607
  81. 1-Wire and Dallas DS1WM in Spartan
  82. OPB timer Microblaze
  83. Problems with GDB in EDK 9.2
  84. ML505 with Petalinux
  85. simulator options
  86. Mobile Users: 4 thins you probably never knew your mobiles can do.
  87. Modelsim Warning
  88. Sythesisable subset of VHDL
  89. New leonardo spectrum version has license errors
  90. GCLK overmapped
  91. How to optimize my design area to fit?
  92. MG Leonardo Synthesis Options
  93. A way to limit the data path delay
  94. Minimum Oscillator Frequency
  95. Possible CRC error on XC3S400 - now what?
  96. 4-bit table look-up
  97. A video tutorial: The Xilinx FPGA Editor
  98. forcing "Unused IOB Pin -> " from .ucf
  99. OFFSET In and hold time
  100. Server configuration for Virtex5
  101. Call For Papers: FPL 2008
  102. Bitstream verification through readback
  103. Scaling data
  104. Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable toset Spartan-3E as target
  105. Internal signal names in ModelSim
  106. Loading from Compact Flash on ML310...
  107. spartan3a support DVI ?
  108. Keeping Xilinx tool from Optimizing out Debugging signals
  109. Xilinx timming analysis
  110. Gemac on ML402
  111. Why use small resistor for Vcco voltage regulator
  112. Loading the design from Compact Flash...
  113. Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9multipliers?
  114. Low Pin Count (LPC) bus code available?
  115. question about fsl and microblaze
  116. Xpower
  117. Design security for pre-Virtex2 parts ?
  118. iru1209 regulator
  119. Xilinx BSCAN primitives proper use
  120. FPGA in Telecommunications
  121. Actel Fusion FPGA
  122. I need a SDRAM controller
  123. new to NIOS II
  124. About 10-bit pixel datum from CMOS image sensor
  125. Xilinx prom programming problem
  126. PC requirements for ISE webpack
  127. ROM/LUT
  128. EPC in Xilinx EDK 9.2
  129. Regarding Hyperterminal
  130. question on record types
  131. difference between net skew in the clock report and clock skew intrce log
  132. Xilinx PAR problem when using chipscope
  133. Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and Virtex 5)?
  134. define a new bust interface
  135. BPSK CORDIC tracking
  136. Spartan3 I/O question
  137. HDLC
  138. Grisoft AVG false positve virus detection in Xilinx software.
  139. Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
  140. regarding DMA memory to memory copy in NIOS II
  141. Power Supply Bypassing Presentation
  142. My first Flash FPGA
  143. equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera StratixII GX-90
  144. Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
  145. Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)
  146. FA: Brand New Altera MasterBlaster up on Ebay
  147. Synplicy and Xilinx - no PAR
  148. Xilinx Spartan 3A/DSP with Coregen 9.2i?
  149. buying fpga kits in denmark
  150. Thoughts about memory controller problems
  151. Endpoint Block Plus v1.5 example design
  152. Endpoint Block Plus v1.5 example design
  153. OV7660 CMOS camera
  154. Fixedpoint Multiply/Accumulate in DSP48
  155. Initialize RAM in IGLOO
  156. Craignell FPGA DIP Module
  157. Adaptive Best Practices
  158. problem simulating in modelsim - swiftpli_mti.dll
  159. Virtex-4 driving a 5V CMOS
  160. XST_BUFFER_TOO_SMALL
  161. Random Number Generation in VHDL
  162. EDK 9.2i install issues in Linux
  163. microblaze question
  164. Craignell FPGA DIL Module
  165. How to choose an FPGA for High speed applications
  166. CFP: DATICS 2008 - Design, Analysis and Tools for Integrated Circuitsand Systems
  167. Type declarations
  168. Altera FPGA
  169. Pwm Sine Generation
  170. Do you know a Reliable PCBA Service Company
  171. data capture
  172. Ballistic chronograph using a Spartan 3E starter board
  173. Matlab code in nios processor
  174. Problem with UART EDK 9.2.02i
  175. FPGA decoupling calculation
  176. Altera FPGA
  177. bi-phase decoding
  178. How FPGA downconvert Giga SPS ADC data?
  179. Sparkfun Spartean3e Board
  180. VHDL Micron memorymodel.
  181. New user of ModelSim XE III v6.2 Starter - problems simulating asimple RAM.
  182. Source of accurate frequency
  183. Fuzzy Fixed Point Calculating
  184. [paper]?FIR on GPU,CPU, FPGA, ASIC
  185. Chipscope Inserter to Chipscope Analyzer
  186. How is FIFO implemented in FPGA and ASIC?
  187. Xpower decoupling network summary
  188. CPLD Pad File
  189. SRL16x2 in Virtex5
  190. When will Xilinx Webpack and EDK support Vista/64?
  191. Quartus-II 7.2sp1 and Systemverilog Assertion SVA?
  192. Using PECL inputs and PLL's in ProASIC Plus.
  193. Two's complement Coregen gone?
  194. Speed of remote JTAG with Quartus jtagd on linux
  195. Xilinx ISE9.2 iMPACT manual
  196. Chipscope compatible with Synopsis or Cadence sythesise tools?
  197. seminars
  198. effect of xray on fpga electronic circuits
  199. CynApps Cynlib
  200. help definining a secure SMARTCARD CHIP BASED, USB UNIT
  201. Documentation on Insight VIRTEX-E Reference Board
  202. Timing Analyzer hangs
  203. Basic FPGA question about Reset
  204. Quartus II Incremental compilation?
  205. V5-SYSMON : MAX6043 suitable?
  206. gaussian filter in Altera FPGA
  207. Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.4. 10base-Ttrouble
  208. User inputs into Spartan-3E starter board?
  209. Question on FPGA
  210. speed... CORDIC vs. pure arithmetic expression
  211. help me about this error
  212. All things ahead, planahead
  213. FPGA Configuration using Multiple PROMs
  214. DCR_INTC usage in EDK - where is SR18804?
  215. ieee_ proposed library
  216. Complex Multiply
  217. FPGA's as DSP's
  218. Help! Micriblase + plbv46_pci in Virtex5
  219. fpga pin to pin conecting
  220. sine and cosine wave generation
  221. sine and cosine wave generation
  222. Debbuging a RISC processor on an FPGA
  223. Where has Xilnet gone?
  224. Read/Write SRAM on Spartan3 Starter kit
  225. libusb-driver and Spartan3-AN Eval kit woes
  226. Virtex4 burn-in failure
  227. Final call for papers
  228. BRAM Readback
  229. Spartan 3AN LVDS I/O
  230. opb_emc_v1_10_b
  231. Timing constraints not applied, ISE & SynplifyPro
  232. Resource utilization broken down by hierarchy?
  233. FPGA evaluation board with > 32K slices
  234. setup ETHERNET UDP link suing spartan-3E starter kit
  235. Is it possible to define an Integer so it could be incremented andreturn to 0.
  236. VirtexE LVDS driver
  237. Feedback on Stratix III
  238. Power up Behavior of Virtex5 IOs
  239. How to view resource utilization by hierarchy?
  240. Place-and-Route : Intel vs AMD
  241. Connecting different FPGAs using LVDS
  242. Cant capture data with Chipscope 7.1
  243. Purchasing IC components at a good price
  244. XAPP924 Doesnt work
  245. Multiple UCF support in Xilinx ISE
  246. Can you help me about SAS IP core implementing
  247. OPB Emac : Sending a frame
  248. How to program and initialize Lattice XP devices
  249. Xilinx ISE 7.1 to 9.2 Width Mismatch
  250. Synthesizing big RAMs