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  1. ddr2 controller for xilinx 1800a dsp starter kit
  2. Simulink(Matlab)/FPGA serial communication
  3. Simulink(matlab)/FPGA serial port communication
  4. Places to visit in Amsterdam and Brussells
  5. ANNC: FPGA Video Interfacing Fundamentals - Revisited - Webcast
  6. VHDL document generation utilities
  7. Is it possible to set Instruction PowerPC Bus ONLY for 32 bits
  8. How to run a block with half the clockspeed on virtex 5
  9. Serial Transmission w/o 8B/10B encoding
  10. How to report LABs' fanout automatically
  11. new Virtex-5 info
  12. Timing constraints in ucf
  13. MP7 and Actel Fusion FPGA
  14. EDK9.2 microblaze tutorial
  15. why Xilinx doesn't support Dual-Rank DIMM
  16. Chipscope analyzer GUI problem in Linux
  17. Re: Remote access to Altera FPGA via jtagd in Linux
  18. Xilinx PLEASE FIX YOUR servers (ISE 10.1)
  19. AWGN in vhdl
  20. BYTE shifter
  21. using mpmc ddr2 controller with an other processor
  22. counterfeit Xilinx ?
  23. High speed memory read and transfer via rocket IO..
  24. Raggedstone1 OEM Pricing now released.
  25. become crorepati in less than one year by trading into indian stockmarket optiontrading.
  26. Viewing internal signals with ModelSim
  27. problem testing the serial interface code from fpga4fun
  28. Actel SX-A Timing Constraints Issues
  29. chip scope
  30. Spartan 3E intefacing for dummies
  31. Synoplify ???
  32. verilog question, break while loop to avoid combinational feedbackduring synthesis
  33. Modelsim XE III 6.x - huge fonts
  34. Is there a means to conditional synthesis in VHDL?
  35. timing and timing reports (again)
  36. Power Estimation of Microblaze (Power PC) based architectures
  37. PCI Express Configuration Testing
  38. Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
  39. Configure Spartan-3E w SD-Card?
  40. SD-Card SDHC artificial 32GB limit
  41. Linux 2.6 PCI Device Driver on Virtex 4
  42. Altera EPM7032S reading checksum
  43. Re: Using TimeQuest Timing Analyzer
  44. DDR SDRAM interface for Virtex II Pro and Spartan3a
  45. ISE 10.0 finally with multi-threading and SV support ?
  46. A Challenge for serialized processor design and implementation
  47. problem with edk9.2
  48. Using TimeQuest Timing Analyzer
  49. Optimizing an inferred counter
  50. serval PCIE issue
  51. vhdl type conversions
  52. to view vhdl variable with gtkwave
  53. SGMII, xps_ll_temac and MDIO / MCD
  54. FSL or DMA w/ FIFO?
  55. IAENG Last Call for Papers (Extended): The World Congress onEngineering WCE 2008
  56. Xilinx interview questions
  57. Chipscope
  58. dual clock fifo
  59. EP2S130F1508C3N STRATIX II FPGA
  60. Intermittent failure to start sw app on pwr-on, SysACE reset doesn'thelp - must cycle pwr
  61. Xilinx Webcase Workflow
  62. total cost for virtex II pro FPGA
  63. Re: Call for Papers Reminder (extended): The 2008 InternationalConference of Manufacturing Engineering and Engineering Management ICMEEM 2008
  64. Designing CPU
  65. implementing ethernet FCS code in verilog
  66. Wondering about "LatticeMico32 Open Source Licensing"
  67. Xilinx impact, boldly going into nightmareland
  68. Need help in SDR
  69. ISE 9.2SP4 error
  70. Call for Papers Reminder (extended): The 2008 InternationalConference of Signal and Image Engineering (ICSIE 2008)
  71. ISSI SRAM.
  72. Xilinx Tristate Registration
  73. Detecting a pulse with minimum width
  74. Help on Virtex-II Pro global clocks.
  75. I need help! Connecting my dual port RAM to a microblaze
  76. Xilinx S3DSP + EDK Board, too good to be true?
  77. DDR3 speed, Altera vs Xilinx
  78. ICMP checksum
  79. Call For Papers with Extended Deadline of March 23: WORLDCOMP'08 (25conferences in comp. sci., comp. eng., and applied computing), July 2008, USA
  80. Actel PA3 with DirectC or SVF, anybody had any success?
  81. Design entries for FSM
  82. simulating Xilinx cores
  83. SDC of NCF?
  84. Problem with Spartan 3 StarterKit
  85. ALTERA SOPC : ptf-sopc files
  86. MAXDELAY="1.0"
  87. Almost offtopic about HDL optimizing.
  88. Xilinx ISE Evaluation DVD 10.1 request...
  89. Using xilinx XAUI core in Ethernet design. What is the exact frameformat pass through XAUI?
  90. microblaze to blockram - Byte-Writes
  91. Temporarely no answer on MEM32 Read request
  92. Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro?ISE isn't seeing it when I try to add new source.
  93. infer block ram with mismatched port width
  94. Xilinx Pipelined Divider for V5?
  95. Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminalwithout Nios2?
  96. Call for Papers Reminder (extended): The 2008 InternationalConference of Information Engineering ICIE 2008
  97. VME 2 Ghz clock generator
  98. Design complexity in Logic cells - Virtex-5 FPGA
  99. avnet virtex-5 lx eval kit ddr problem
  100. Could I develop a new gui using java based on the script language ofChipScope?
  101. Ann: New FPGA beginner's Video guide
  102. BRAM synthesis question
  103. Matlab, RS-232, Ethernet
  104. Contradicting messages from Xilinx' place and route/timing analyzer
  105. Virtex-5 FX when ? (III)
  106. vhdl code realization
  107. its regarding to the Max Frequency in xilinx FPGA
  108. Virtex-4 VLX25 DCM problem
  109. Trying to contact Jeung Joon Lee
  110. New Release of VPR, Version 5.0 Beta
  111. share the knowledge of about intel pentium processor and processingspeed....
  112. opencores down ?
  113. 2nd CFP: DATICS 2008 - Design, Analysis and Tools for IntegratedCircuits and Systems
  114. Hardware Cosim one wrong output and one correct output
  115. Cyclone III and Quartus 7.2sp2
  116. Datasheet on Micron's secure products
  117. Danger of having JTAG TAP controller always enabled in Xilinx parts
  118. SiliconBlue enters the FPGA fray
  119. ML523 power module schematics
  120. Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
  121. Fixing design, leaving BRAMS variable
  122. Spartan-3A DSP Starter: JX Connector Part number
  123. Xilinx MIG2.0 DDR2 memory controller
  124. how to Load file data into memory by NIOS II IDE?
  125. XC3S50-4VQ100C fpga chip
  126. MicroBlaze MMU support test release now available
  127. 802.16d with Xilinx Viterbi Decoder
  128. I could run my program at DDR Sdram.
  129. Call For Papers with Extended Deadline of Mar. 15, 2008: The 2008International Conference on Communications in Computing (CIC'08), USA, July2008
  130. Call for Papers: The 2008 International Conference on Parallel andDistributed Processing Techniques and Applications (PDPTA'08), USA, July 2008
  131. Call for Papers Reminder (extended): The 2008 InternationalConference of Computational Intelligence and Intelligent Systems (ICCIIS 2008)
  132. how to optimize a design for speed
  133. question about verilog language constructs
  134. could use some help with verilog/vhdl
  135. Call for Papers with Extended Deadline of Mar. 10, 2008: The 2008International Conference on Embedded Systems and Applications (ESA'08), USA,July 2008
  136. Anyone to open "FPGA museum" ? Here is first item :)
  137. Virtex 5
  138. Spartan-3E + SPI EEPROM
  139. PCI Timing Contraints ignored
  140. EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
  141. Bit Error Rate Test
  142. Re: Blast from the past
  143. Call For Papers with Extended Deadline of Mar. 10, 2008: The 2008International Conference on Wireless Networks (ICWN'08), USA, July 2008
  144. AES Bitstream Encryption in Virtex-4. How safe it is?
  145. [Altera] How to infer some code into ROM-blocks (in automatic way),but not all
  146. FPGA for a DVB common interface implementation
  147. FPGA for a DVB common interface implementation
  148. PARAMETER C_SPLIT error
  149. Call for Papers (Extended): World Congress on Engineering WCE 2008
  150. reconfiguration of virtex 2 pro
  151. verifying UNIFORM using matlab
  152. "Use Multi-level Logic Optimization" -- Advanced Fitting option
  153. my Spartan-4 wishlist
  154. ICAP for readback on Microblaze...
  155. ICAP for readback on Microblaze...
  156. clock distribution accross boards
  157. Virtex-5 FXT coming soon?
  158. FPGA/CPLD group on LinkedIn
  159. Synplify crashing
  160. Call for Papers with Extended Deadline of Mar. 10, 2008: The 2008International Conference on Computer Design (CDES'08), USA, July 2008
  161. clock generation
  162. Avnet/Memec V4FX12LC proto card and SysGen
  163. Call For Papers with Extended Deadline of Mar. 10, 2008: The 2008International Conference on Grid Computing and Applications (GCA'08), USA,July 2008
  164. FPGA's be afraid, very afraid, of my wife!
  165. Quartus 7.2sp2 memory exhaustion
  166. HELP > Face/Edge detection on FPGA
  167. Need info on systolic arrays in actual use
  168. real to signed
  169. DSP Ip Core
  170. Is there any way to disable JTAG for Sptantan3AN
  171. Re: What demokit and VHDL compiler pair to buy
  172. What demokit and VHDL compiler pair to buy
  173. Re: Picoblaze enhencement and assembler
  174. Software for FPGA-based PC scope
  175. DCM Simulation : Input Clock Cycle Jitter
  176. Call For Papers with Extended Deadline: WORLDCOMP'08 (comp. sci.,comp. eng., and applied computing conferences), July 2008, USA
  177. DSP newbie
  178. DSP newbie
  179. Making changes to custom IP in EDK
  180. sd card slave interface
  181. sd card slave interface
  182. Using dma_sg_v2_01_a component with plb_ipif
  183. Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
  184. Quicksim/modelsim
  185. ICAP attached to Microblaze on Virtex 2-pro..
  186. Why must a V4 be configured within 10 minutes of power up?
  187. ANNC: ADC to FPGA Interface Webcast
  188. ASAP 2008 Submission deadline extended till 5th March'08
  189. Xilinx's microblaze hangs when a timer interrupt occurs after a"rand()" instruction.
  190. Tomorrow at Embeded in Nurnberg: Portable XSVF player demo
  191. SPI indirect programming using spartan 3e
  192. How to connect FPGA to a ASIC Board?
  193. Viewing RTL schematic in Xilinx ISE
  194. OPB_MDM as UART in a PowerPC design
  195. Preventing optimization in cross clock domain logic
  196. Convert some table into combinatorial circuit + optimization
  197. ModelSim Natural arg value is negative
  198. set_input_delay min and max (timequest)
  199. Typical jitter of high frequency oscillators?
  200. Using ICAP in s3a to reconfigure
  201. Hardware Cosim no output
  202. Does Altera has some analogous file like XDL of Xilinx?
  203. Synthesis of functions in Quartus
  204. sFPDP IP Core
  205. Xilinx parallel cable 4 clone
  206. About John Williams' ICAP driver?
  207. Picoblaze enhencement and assembler
  208. Seed Values
  209. The Java processor JOP is now GPL
  210. Online Engineering Calculator Tool for Electronic Engineers - FREE touse
  211. Command to unzip hardware cosim files
  212. XEM3010
  213. more microblaze firmware blues. tool chain version problem?
  214. canny edge detection
  215. canny edge detection
  216. Planahead IP export
  217. FPGA Editor Tutorial based on examples
  218. Xilinx DCM for frequency synthesis -- newbie question
  219. Problem with PINs XC3S700A-4FG484
  220. newbie seeking help to use xilinx spart-3a starter kit
  221. Actel FPGA programming using libero 8.1 generated SVF files
  222. Xilinx self-termination
  223. Software Defined Radio on Xilinx Virtex 4
  224. How to use xilinx specific features from Modelsim Designer 6.3a VHDL
  225. Interview questions
  226. Software Defined Radio auf Xilinx Virtex 4
  227. which IOSTANDARD to use for IO-bank in Spartan-3
  228. Reconfiguration (on the fly) using SPARTAN 3A
  229. System generator hardware co-simulation interface
  230. ADPCM IP Core
  231. V4FX: LVCMOS25 vs LVCMOS33 output buffer
  232. Interrupt Handler page missing in from software platform settings inXPS 9.2i
  233. Post PAR simulation is successful but still fails on the board
  234. From ASIC RTL to FPGA, what are the things I should take care of?
  235. Re: scanf problem in EDk 9.1i (Microbaze)
  236. scanf problem in EDk 9.1i (Microbaze)
  237. Virtex5 BUFR min frequency
  238. Which Linux Distro to use for Xilinx tools
  239. FPGA Programming solution
  240. MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
  241. Efficient division algorithm?
  242. Using Lattice ispLEVER with VHDL libraries
  243. TCL testcase in Modelsim.
  244. Re: Ballpark PLB frequency
  245. V4FX100 PowerPC PLB issues (and EDK 9.2)
  246. Define the primary clock with XST in VHDL
  247. MicroBlaze simulator, software ownership rights for SALE
  248. Interface on board ADC to Spartan 3E startkit
  249. Antti needs a job
  250. Embedded in Nurnberg