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  1. Cyclone 3 on chip termination
  2. xilinx spi core question (microblaze)
  3. FPGA imp
  4. How do I get Xilinx EDK to load a 'custom' XBD file?
  5. Re: demo board under 500usd
  6. problem in using ICAP
  7. demo board under 500usd
  8. xilinx beginner modelsim question
  9. About the user defined instruction in APU
  10. Yay! We're done with the quadrature encoder!
  11. power supply noise margin
  12. Need help on ASIC/ASSP FGPA-based prototyping and verification survey
  13. Re: Problem with PlanAhead on Partial Reconfiguration on ML403(Virtex 4)
  14. xsa-50 issues
  15. Programming XCR3064xl - voltage at output stuck at 0
  16. value of the weak pull up resistor on IOBs of Virtex5
  17. Is Virtex 4 supported by Jbits ?
  18. How to input an analog signal to FPGA board for processing?
  19. has anyone made PLB_DDR work with 1Gb DRAM chips?
  20. RLC package parasitics
  21. how to set trigger in ChipScopePro for this
  22. Xilinx ML507 evaluation board (V5FXT70)?
  23. getting samples from an RF board onto the system
  24. USB full speed final project proposal
  25. Conversion from VERILOG READMEMB to INTEL HEX
  26. udp receive problem under nios
  27. ISE 9.2 - how do I extract component/slice placements for lockingdown a design?
  28. Vritex2PRO: LVDCI for inputs?
  29. Xilinx Platform USB Cable II
  30. 5 V oscillator output to GCLK
  31. SDIO CRC7 + VCD waves
  32. AHB and APB master VHDL generator
  33. Anyway to secure a Xilinx NGC file ?
  34. Spartan 3 Mapping Problem
  35. Virtex XCV1000E-6FG860C
  36. ML300 evaluation board broken?
  37. Quartus 7.2 and PCI Express
  38. Dual rank DDR2 memory for Xilinx ML410 board
  39. EDK for spartan2?
  40. Re: PCI Express Switch
  41. Re: Chirp generator / CORDIC algo ?
  42. ps2 mouse protocol
  43. Does anyone have sdio protocol experience?
  44. DSP48 Inference Template for XST
  45. NGC / EDIF Viewer
  46. FPGA dev kit with 4-8 Cyclones or Spartans
  47. Call VHDL module from Verilog
  48. warning from ISE 9.2
  49. Getting started with VHDL and Verilog
  50. BRAM initialization / bitstream configuration
  51. How program PROM from msc file
  52. Using Sysgen v8.2
  53. Xilinx ISE 10 in CentOS not showing in application menu list
  54. Looking for FPGA/CPLD skills to develop prototype
  55. Silicon
  56. Re: NIOS II CFI interface
  57. EDK9.2i simulation problems.
  58. need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area
  59. FPGA Processor for Signal Processing ?
  60. Using SRL16
  61. Aldec Active-HDL 7.3 sp1 [stimulators]
  62. Re: Old FPGA question
  63. Forking in One-Hot FSMs
  64. Re: Style for Highly-Pipelined State Machines
  65. Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
  66. Re: xilinx remote platform flash program
  67. Re: Virtex4 Output Pins during Configuration
  68. Re: quick question
  69. Re: Quartus v7.x fitting bug
  70. Darnaw1 Schematics
  71. How to embed time and date in Xilinx FPGA?
  72. what's next?
  73. Nano transistor breakthrough?
  74. Quatech SPP 100 PCMCIA to Parallel Adapter for FPGA Board for Sale
  75. how can i recover my unencrypted bitstream starting from encryptedone and knowing the KEY
  76. CRC algorithm
  77. Virtex-4 inrush power-on current
  78. How to arrange these SRL16 in a straight column
  79. Spartan3 "commercial" temperature range
  80. Breaking News ... Accellera Verification Working Group Forming
  81. Timing closure problem --- how to make the QII fitter smarter
  82. PLB Master Example
  83. V5, EMAC simulation problem, when 4 EMACs are used together (ISE10.1, ModelSim 6.3d)
  84. noob question
  85. delta sigma adc.....
  86. ATF750 for Proteus
  87. ANNC: Digital Power Management Webcast
  88. ACTEL FPGA static timing analysis
  89. HydraXC + EDK
  90. video stream transfer via UART and Bluetooth in FPGA
  91. will there be any problem with diffrent version of sysgen & EDK
  92. superscalar processor design
  93. FPGA comeback
  94. Verilog state machines, latches, syntax and a bet!
  95. 10.1 EDK - How can I create a user library in SDK?
  96. the order in which some switches are turned on
  97. Can somebody help about Period Timing Constraints
  98. FPGA Verilog state machine lock up
  99. Xilinx is cancelling the Virtex-E XCV1000E-FG860
  100. Need a few Xilinx Spartan FPGAs
  101. How to independently program the embedded PowerPC in a Virtex?
  102. Altera Cyc II config problems
  103. Newbie: Testbench question
  104. Turning off the DLL to run DDR2 at very low frequency
  105. opb_intc + PowerPC
  106. not inferred RAM, on QII
  107. DCM configuration in Virtex-4 FPGA
  108. Celoxica RC1000
  109. OPB_MDM functionality
  110. XmdStub fails when connecting via JTAG.
  111. ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
  112. Problem writing quadrature decoder
  113. synchronous reset problems on FPGA
  114. how we can prove that really the AES 256 is used to crypt theBitstream in virtex 5
  115. Very simple VHDL problem
  116. Synthesis Comparison
  117. How to instantiate macro in verilog
  118. Xilinx DDR2 Interface
  119. Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
  120. Chipscope is Failing
  121. New to FPGA : Timing Closure
  122. Chip photos of old FPGAs
  123. XST design frequency setting
  124. Survey: FPGA PCB layout
  125. attached a 2nd peripheral to FSL bus. how to use it in software?
  126. UK Embedded Masterclass
  127. DMA in PLB custom core (XilinxV4)
  128. Help, router can't rout all connections (XILINX)
  129. how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
  130. Wishbone, TSK3000 and endianness problem
  131. ICAP_VIRTEX4 primitive
  132. chipscope pro , lower level signals not visible
  133. 91c111 drivers for NIOSII without ucosII/lwip stack
  134. Virtex 4 DCM problem
  135. Help Need about reconfiguring the PLL with prescale counter n andmultiply counter m
  136. asic gate count
  137. Inconsistent File Reading/writing in binary format using MicroBlaze
  138. Snythesis error
  139. Pre and Post Synthesis Simulation mismatch
  140. Simulation tools for Xilinx ISE
  141. Xilinx JTAG Linux programming
  142. "Multi-source in Unit" Verilog synthesis woes
  143. DOS script file to synthesize a VHDL design
  144. Actel Cortex
  145. Which to learn: Verilog vs. VHDL?
  146. Chipscope 9.2 in XPS
  147. XST support for User Defined Primitives
  148. HiTech Global Eval boards?
  149. Question about Spartan 3E starter kit
  150. become crorepati in less than one year by trading into indian stockmarket optiontrading.
  151. Spartan3E startup problems
  152. simple example with timing problems
  153. CF (systemace) SD card, etc performance
  154. Need help on UNISIM.Vcomponents.all
  155. high noise/signal in a simple serial to mono dac module
  156. Virtex4 FX PPC and Fsl
  157. ISE 9.2 and Windriver
  158. case statements- verilog to vhdl
  159. 64 bit WebPack
  160. Xilinx tech Xclusive
  161. Xilinx ISE synthesis error (error:3524 Unexpected end of line.)
  162. Split register in smaller segments
  163. Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
  164. why to trigger a NMI error after just receiving 35 pakcets?
  165. You M.ust know this to get Financial Aid!
  166. clock instanciation
  167. Specifying strict setup constraint in ISE
  168. Xilinx FFT C-sim model
  169. Xilinx CPLD programming tool under Linux
  170. Task in verilog
  171. looking for critique for a spartan3a lcd controller verilog module
  172. ANNC: Verilog Coding for FPGA Webcast
  173. Disable optimisation - Ring oscillator
  174. 32 bit multiplier
  175. Starting a PCI Express Application
  176. Intel plans to tackle cosmic ray threat
  177. NoisII or else.
  178. OBUF gate delay
  179. MIG/Corgen to XPS core insertion
  180. Avalon Bus <-> Wishbone Bus
  181. Modify POF with new ESB (ROM) content?
  182. FPGA configuration mode on ML310
  183. 19th IEEE/IFIP Rapid System Prototyping Symposium
  184. Xilinx xilfatfs and systemACE speed issue
  185. system level language: why all this fuss about
  186. Use of floating point numbers in xilinx EDK .........
  187. problem with synthesis of a state machine
  188. PLA datasheet - PLS161
  189. Project Ideas
  190. Xilinx inferred FIFOs
  191. UK Embedded Masterclass
  192. Examples for Spartan3 StarterKit
  193. Xilinx FPGA + SMPS
  194. One more question. WebPACK key with ISE
  195. loop back on a MARVELL switch
  196. Downloading some data from flash memory thru JTAG.
  197. problem with synthesis
  198. synplify pro generates negative slack
  199. No synchronization word in prom file (XILINX)?
  200. Spartan3 JTAG flash In System Programming over Ethernet
  201. Beginner's silly question about ICAP
  202. Protecting design from being downloaded on other (similar) FPGAdevices
  203. EDK 10.1 first impressions
  204. Conterfeit parts guidance
  205. ModelSim XE problems with a VHDL coregen in a Virtex 5
  206. Xilinx ISE 10.1 Ubuntu Linux Installation - Driver InstallationProblem
  207. Xst_Choice nodes
  208. "Number of BSCANs: 2 out of 1 200%"
  209. coregenerator bram in synplify pro error
  210. Why does ISE 9.2 optimize out the logic
  211. now I can talk about it...
  212. ISE 9.2i project question
  213. Simple (?) timing constraint for output pins
  214. Xilinx and Modelsim?
  215. Partial reconfiguration by using ICAP
  216. Impact won't program XC3S200, does program XC3SD1800A
  217. become crorepati in less than one year by trading into indian stockmarket optiontrading.
  218. JTAG: First of 4 Spartan-3E always UNKNOWN
  219. Welcome to our world - Blog
  220. ISE 64 bit
  221. increase memory of microblaze
  222. Using USB programming cables from Xilinx and Lattice on one Windowsmachine
  223. Writing to DDR RAM on Virtex II Pro Board on PLB Bus
  224. fpga reset (re-initialize) of spartan3e
  225. System Generator Error
  226. Synthesisable Timer in VHDL
  227. After reset, the PC register of PPC is not back to 0Xfffffffc
  228. Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1
  229. ISE 10.1 - Initial experience
  230. async clk input, clock glitches
  231. Newbies: Answer to "What is an FPGA?" in video
  232. FPGA beginner video guide, blog comments by Max Maxfield
  233. Having trouble building an old Xilinx Spartan3 FPGA project I did onISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
  234. Can't read external Flash in a V4 based PPC system through gdb
  235. Webpack 10.1 on 64-bit linux
  236. quick question
  237. ISE 10.1 XST runs in background?
  238. problem with uartlite in microblaze
  239. Sorry to Those Who Deem This to be Spam: Employment or ScholarshipSought
  240. JavaBotics Marmaduke board
  241. PCI Express Switch
  242. CAM implementation using Dual port ram
  243. FPGA board with an ADC
  244. Re: problem simulating in modelsim - swiftpli_mti.dll
  245. need help.....how do i download an image onto a virtex 4 fpga
  246. Dual Independent Aurora Links on One GTP Tile
  247. [CORRECTED] Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
  248. Sub: Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
  249. zpu processor core
  250. Xilinx ISE 9.2i out of memory