PDA

View Full Version : FPGA


Pages : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 [33] 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

  1. Lattice vs Altera (Mico32 / NIOS)....or?
  2. Rebuilding harware for Petalogix Linux
  3. Virtex 5 DSP48E Instantiation.
  4. Mismatch between XST and trce delay estimation
  5. Virtex-5 clocking
  6. More Actel 'Funnies'
  7. how to share infered ROM memories in synplify?
  8. ChipScope on Ubuntu 7.10 - blank screen
  9. Update Altera MAXII UFM post production
  10. Xilinx VHDL inferred RAMs
  11. I need a good reference for VHDL
  12. MUX Inference
  13. How to synthesize a delay of around 10 ns in FPGA?
  14. Packet sniffer help
  15. Input to FPGA boards
  16. Those FPGA boards
  17. Newbie question
  18. Actel constraints?
  19. FPGA / DSP Jobs
  20. trigger problem with chipscope
  21. Looking for an FPGA board with large memory and high speed interfaces
  22. learning videos for xilinx edk tools
  23. learning videos for xilinx edk tools
  24. Re: ISE Question - FPGA Program.jpg (1/1)
  25. Connecting MPD I/O ports in xps_sysace
  26. Reading files from CF (microblaze 7 and plb)
  27. Barrel Shifter: Newbie's Attempt
  28. Spartan 3E overmapping problem
  29. ISE Question - FPGA Program.jpg (0/1)
  30. A question about the use of FPGA
  31. Xilinx cores with license
  32. OTU2 implementation with Virtex 4
  33. Virtex-5 Integrated Endpoint Block for PCI Express Designs
  34. Xilinx PCIE problem
  35. Bitstream configuration question (virtex 5).
  36. Video processing in FPGA
  37. Xilinx PCIE problem
  38. Do two clock system blocks with one clock running half of other'sneed asynchronous input/output buffers?
  39. synopsys designware components on xilinx fpga
  40. Virtex-5 DDR2 DCI termination
  41. WEBPACK for linux
  42. Two questions about Xilinx constraints setting
  43. Standalone Altera production programmer
  44. Call for Papers: IAENG International Conference on ArtificialIntelligence and Applications (ICAIA 2009)
  45. floating point round off errors
  46. spam
  47. Re: which FPGA chip to use for FFT?
  48. Xilinx device not listed
  49. Gee Thanks Altera, I really enjoy having a break waiting on yourlicense server
  50. Asynchronous delay report shows delays longer that clock period - ok?
  51. Post-synthesis simulation
  52. spam
  53. reasonable timing analysis without mapping design to IO
  54. Interfacing DDR RAM
  55. $99 XMOS Dev kit
  56. if data moves faster faster than the Clock....
  57. spam
  58. spam
  59. spam
  60. Problem with mpmc(4.02.a) simulation -- DDR never initializes
  61. pciAutoConfiguration on MVME5500
  62. Re: Sending UDP packets over Ethernet
  63. Sending UDP packets over Ethernet
  64. short announcement for TimingAnalyzer
  65. Low frequency clock generation - need help
  66. Difference between PLD and General purpose CPU`
  67. Looking for Insight S2-PCI w/XC2S150 board documentation/manual
  68. Open source IP core development with configuration GUI
  69. Does XST support global signals?
  70. maximum clock rating
  71. Clocking Sync Burst SRAM
  72. spam
  73. Call for Papers: International MultiConference of Engineers andComputer Scientists IMECS 2009
  74. MicroBlaze SMP system DEMO
  75. Having problems with using flash in EDK
  76. Please recommend good textbook or technical report about FPGAcoprocessor
  77. wishbone interface
  78. FPGA Lab Liquidation Sale
  79. Weird DCM problem with external deskew
  80. decimal to ieee 754 single precision floating point
  81. Simulating BRAMs using ISE simulator?
  82. Xilinx Mode Select Pins
  83. OFDM band switch ...
  84. Use of divided clocks inside modules
  85. duty cycle significance
  86. Avalda's Parallel F# to RTL FPGA Compiler
  87. Ethernet MDI termination
  88. Xilinx Timing constraint problems
  89. HDL Companion
  90. 50 Ohm Analog Output of FPGA
  91. ISQED 2009 call for papers
  92. Altera and DDR3
  93. Is it possible to get an RTL netlist from Xilinx tools?
  94. Virtex-II Pro to Stratix GX
  95. Is it hard to detect an ucf sytax error?
  96. WebPack on CentOS 5 ?
  97. spam
  98. Synplify Pro derived clock going out as port
  99. Peter says Good Bye
  100. What software do use big organizations for Logic Synthesis from HDL?
  101. usb on a spartan
  102. Help~ How to develope with FPGA board?
  103. Clock Enable safe?
  104. interview questions ........
  105. Two-complement value from ADC, Spartan-3A, 3E
  106. SDRAM question
  107. 1QN representation
  108. Random Mask Generation on FPGAs
  109. Free H/W Co-sim solution (Call for Wiki participation)
  110. Xilinx Spartan E
  111. security system password by voice recognition commands
  112. Info request about Synplify and Foundation usage
  113. Two JTAG Parallel IV Cable in a single PC.
  114. spam
  115. Compiler Options
  116. Xilinx build system
  117. Ethernet and Interrupts in Virtex II pro
  118. spam
  119. Moving to Altera from Xilinx
  120. spam
  121. Some random impressions from FPL 2008
  122. Xilinx FFT core configured in natural order
  123. ASIC Prototyping
  124. Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
  125. Problem with Virtex-4 IBIS model
  126. Interfacing external memory
  127. Ultra low power FPGAs
  128. Quartus II compile speedup with New Quad Core Intel machine (comparedwith old dual XEON workstation)
  129. errors in schematics
  130. How to install Xilinx ISE simulator?
  131. Load Application from External Memory without the use of XMD???
  132. WinCupl Problem(s)
  133. Spartan-II, config pins 5V tolerant? (slave serial)
  134. Can Soft microprocessor replace DSP's
  135. IDELAYCTRL Locking problem with ISE10.1i
  136. spam
  137. What version of ISE is availabe for Virtex5?
  138. Placing Verilog busses using Xilinx RPMs
  139. spam
  140. Altera Serial Lite Protocol implemented on Xilinx ??
  141. Vista 64: USB drivers still don't install
  142. IEEE 1394 interface for FPGA??
  143. No connect pins on xc4vfx20
  144. Signed multiplication
  145. Spartan 3E evaluation board manufacturers
  146. LVDS Receiver in FPGA
  147. Some feedback on the Xilinx web site
  148. Best way to buy Xilinx FPGAs?
  149. Are Xilinx tools that bad, or am I missing something?
  150. Altera library sim question
  151. Reviewing Equation information on Altera Quartus II version 8
  152. need sme help on data encryption based on fpga
  153. uClinux / Microblaze -- Min. Requirements
  154. Spartan-3 -> Spartan-2 problem
  155. Hide VHDL code.
  156. EDK frequency problem
  157. Strange Spartan2 behaviour
  158. LED lights flashing while LCD shows chars, Spartan-3A
  159. XST bug on illigal states of a FSM ?
  160. request for beta testers -- TimingAnalyzer Program
  161. Quartus II priority 19 under Linux
  162. what is the maximum number of DDR controllers
  163. Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
  164. FPGA package size chart (smallest) Xilinx holds 8th place
  165. how to built a CCD camera + FPGA ???
  166. Is it possible to do incremental synthesis and placement?
  167. ED 9.2 too new cygwin error
  168. FPGA on a DIMM module, performing encryption
  169. Serial port issues with Matlab
  170. ONLINE RESOURCE FOR HELP DESK SOFTWARE
  171. Xilinx Multipass PPR
  172. Re: Future architectures [was Re: Intel details future Larrabee ...]
  173. Format of Actel's SVF files
  174. crazy patent
  175. How many mux input on a Xilinx V4 are pratical
  176. How to disable the static routing to cross through the PRR?
  177. Mass storage device on ML403 board
  178. Timing analyser
  179. genügt das fürs erste?
  180. Virtex 5 bitstream encryption
  181. Genode FPGA graphics project launched
  182. FPGA/CPLD Design Group on LinkedIn
  183. Saving PAR Constraints
  184. Side-BUFG, BRAMS and clock routing
  185. Xilinx Virtex 4 Newbie
  186. xlicmgr vs lmutil/lmstat and floating licenses
  187. AES decryption (ASIC)
  188. Verification methods importance
  189. need fast FPGA suggestions
  190. Analog Imager interface to FPGA
  191. Writing data on CF card using EDK 10.1 and xilfatfs
  192. Problem in simulating Xilinx MPMC in VCSMX
  193. Top 10 Things To Look For In A Web Host
  194. Sample vhdl to write and read a value from a Spartan 3 block ram?
  195. Digital-to-Analog Converter LTC 2624, Spartan-3A
  196. Scripting xsvf generation?
  197. Virtex 5 evaluation boards
  198. missing Xilinx virtual machine Centos password
  199. Apple II on FPGA
  200. How to "propagate" a serial signal
  201. ADC7874 Timing violations
  202. Image input
  203. VHDL models for DDR2 SDRAM?
  204. Workaround for installing EDK on Vista x64?
  205. need efficient multichannel DDC on V4
  206. Xilinx extends Spartan 3A series
  207. part time jobs
  208. FPGA Videos - Olympics Celebration Sale
  209. ML403 PPC and ISE tools: timestamp and <sysace_stdio.h>
  210. fun with indian *** moves downloadfree
  211. Setting a control parameter in Active HDL
  212. Spartan-3AN JTAG problem
  213. More work, less posts
  214. MJL Cyclone Development kit and Quartus II
  215. Ultracontroller-2 on ML403
  216. How to see the contents of BRAM in simulator?
  217. Multicore OS
  218. A timing question
  219. why does inferred RAM cause synthesis times to explode?
  220. Verilog modules and stimulus in same file
  221. Q: Demo Altera NIOS II SOPC limitations
  222. video timing with TFP410
  223. spam
  224. Question on V4 HSPICE model
  225. 512MB DDR2 533mhz registered dimms
  226. Real port types in VHDL
  227. Hardware in Loop
  228. XMD & Ultracontroller
  229. Again: EDK10.1 and TEMAC - I'm despairing
  230. Microblaze Projects
  231. Using a Spartan 3 FPGA kit with a USB/DB9
  232. ANNC: PCI Express with FPGA Webcast Tomorrow
  233. [Xilinx]:SetClbBits() function in HWICAP
  234. SDIO open source code
  235. spam
  236. Optimizing a LUT-based pow(val, 2.2)
  237. spartan sa dcm maximal frequency
  238. Altera question - MAX3000 vs MAX7000
  239. Newbie question : Xilinx Webpack examples
  240. Spartan 3e, LVDS LCD.
  241. Block Rams
  242. altera cyclone3 vertical migration
  243. eliminating individual array registers?
  244. Coolrunner programming - best way?
  245. altera cyclone3 484BGA package
  246. Development board with SD card.
  247. need analog ntsc - ccir 656 core
  248. Perot, IBM, Hewlett-Packard, Dell, Wipro, HCL, Infosys, Satyam Hiringsoftware Engineering candidates and MBA candidates
  249. Altera Cyclone and Stratix II
  250. Nibz processor @ 472 LEs (16 bit generic specified)