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Old 12-07-2009, 11:43 AM
avinashthakare avinashthakare is offline
Junior Member
 
Join Date: Dec 2009
Posts: 1
Default Create vcd file from raw data

Hi All,

I'm running design on FPGA and the output data of design is dumped on my host machine as raw data.
For example : design has 2 outputs "a" & "b".
and on every clock a & b data in dumped on host machine as shown below.
######
MSB represents "a" & LSB represents "b"
######
10 -->first rising edge of clock
01 -->second rising edge of clock
11
00
10
11
######

I would like to know if you have script which converts this raw data into vcd file so it can be viewed in modelsim or anyother simulation which supports this format.

Thanks
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