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Old 10-10-2006, 08:57 PM
Andrew FPGA
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Default Re: Generics vs Constants - what criteria do you use to choose between these?

Andy wrote:
> I've found a very interesting hybrid approach to managing constant
> design parameters, but let me summarize some pro's and con's of
> constants vs generics.
>
> Comments?


A single record generic is an interesting idea but the main issue I
have with it is that it makes it harder to look at an entity and see
straight away what has been paramatised for this entity. With a
complete generic parameter list at the top of the entity its
immediately obvious what aspects of the entity can be configured.

I'm also worried about global namespace issue, its sort of like the
reverse of encapsulation, all the parameters are spread to all
entities/modules.

Generics vs constants:
I'm starting to form the opinion that most all paramaters that
statically configure an entity should be in the generic list (or the
port list in the case of Mike Treselers method). I can only think of a
few exceptions:
1) static configuration that affects almost all entities/modules across
the project and that must take on the same value for all
entities/modules. Even the clks_per_tic doesn't meet that requirement,
although its a design goal to minimise the number of clks, its hardly
ever 1.
2) static configuration that affects a group of entities that can be
put into a package that only that group of entities include. E.g.
parameters for an optical link, like frame length, frame sync word etc
where the optical link is implemented with several entities(say a
receive framer, transmit framer etc).

PS: I quite like Mike Treseler's method of using just normal port
signals instead of generics. One advantage I can see if in the future
you want to dynamically control the behaviour, just wire the port
signal up to a cpu register bit, no change to the entity required. If
you want it static just hold the control constant and synthesis
optimises the control logic away.

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