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Old 10-09-2006, 07:42 PM
Mike Treseler
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Posts: n/a
Default Re: VHDL count error when cascading

rob wrote:

> Can anyone give me some insight into this error.


I don't understand the requirements,
but here is a cleaned up version to look at.

-- Mike Treseler
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity segment_cnt is
port(

clk, mr, en, pause, clk_in : in std_logic;
segs : buffer std_logic_vector(6 downto 0);
rco : out std_logic
);
end segment_cnt;

architecture behav of segment_cnt is
begin
cnt_proc : process (clk, mr) is
begin
if(mr = '0') then
segs <= "0000001";
rco <= '1';
elsif rising_edge(clk) then
if(en = '0' and pause = '1') then
case segs is
when "0000001" => -- 0 goto 1
segs <= "1001111";
when "1001111" => -- 1 goto 2
segs <= "0010010";
when "0010010" => -- 2 goto 3
segs <= "0000110";
when "0000110" => -- 3 goto 4
segs <= "1001100";
when "1001100" => -- 4 goto 5
segs <= "0100100";
when "0100100" => -- 5 goto 6
segs <= "0100000";
when "0100000" => -- 6 goto 7
segs <= "0001111";
when "0000111" => -- 7 goto 8
segs <= "0000000";
when "0000000" => -- 8 goto 9
segs <= "0001100";
rco <= '0';
when others => -- 9 goto 0
segs <= "0000001";
end case;
end if;
end if;
end process cnt_proc;
end behav;
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