I am trying to generate a clock signal and other stimuli in this
testbench. What am I doing wrong about the clk generation? I get and
error duing run time simulation, because of that line. I've used the
clock generation code before without a process for other stimuli, and
it worked great, but now, what gives?

# ** Error: (vsim-3601) Iteration limit reached at time 0 ns.


--================================================== ===============
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY fsm1_tb IS
END fsm1_tb;

ARCHITECTURE fsm1_tb_arch OF fsm1_tb IS

COMPONENT fsm1
PORT(w, clock, reset: in std_logic;
z: out std_logic);
END COMPONENT;

CONSTANT clkperiod: TIME := 1 ns;
SIGNAL test_w: std_logic;
SIGNAL test_clock: std_logic := '0';
SIGNAL test_reset: std_logic;
SIGNAL test_z: std_logic;
SIGNAL value: std_logic_vector (0 TO 17) := "010111100110011111";

BEGIN
UUT:fsm1
PORT MAP(w => test_w, clock => test_clock, reset => test_reset, z
=> test_z);

test: PROCESS
BEGIN
test_reset <= '0';
FOR i IN 0 TO 17 LOOP
test_w <= value(i);
WAIT FOR 1 ns;
END LOOP;

test_reset <= '1';
WAIT FOR 1 ns;
test_reset <= '0';
END PROCESS test;


test_clock <= NOT test_clock AFTER clkperiod/2; --CLK Generation

END fsm1_tb_arch;
--================================================== ===============

P.S. Yes I am a noob.