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Old 09-21-2006, 05:50 PM
Posts: n/a
Default Re: VHDL language question regarding placement of attributes

I did run across some more info (link below) that would seem to
indicate that prior to VHDL-2002 entities and their corresponding
architectures form a single declarative region.

Per Synplify's online help...

The language information is taken from the most recent VHDL Language
Reference Manual (Revision ANSI/IEEE Std 1076-1993)

This would seem to indicate two things:
- My beef is with Synplify for the error that I'm getting and that
Synplify does not conform to the 1076-1993 standard in this
regard...although perhaps it is conforming to the 2002 standard.
- Somebody needs to send Synplify a copy of the 2002 and 2006 manuals
if they think that 1076-1993 is the 'most recent'.

Also, the link above seemed to indicate that future revisions of the
standard would probably try to fix what they broke by doing this.
Since the 2006 standard has just come out maybe it does.

If anyone who can interpret the LRM better than I can comment I would
still appreciate hearing about it.



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