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Old 09-21-2006, 05:45 PM
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Default VHDL language question regarding placement of attributes

Can someone point me to the appropriate verbage in the LRM that
supports or refutes the following statement copied from Synplify's help
manual. I have code of the type that Synplify lists that compiles with
Modelsim and Quartus without complaint but Synplify gives the warning
so I'd like to know, per the LRM, who is correct? Synplify or

The Synplify online help goes on to explain how they believe the
attribute declaration belongs inside the entity but I'd like to know
which tool is not correctly interpreting the standard before


-- Snippet of online help from Synplify 8.5.1
@W: No such identifier, <q2>, of proper type in current declarative
VHDL Compiler Warning CD134

This warning occurs when the compiler finds a signal that is used in an
attribute, but not declared within the corresponding declarative
region, such as between the architecture definition line and the begin.
In the test case below, qrs is not defined within the declarative

entity dff1 is
port (data, clk, reset, set: in std_logic;
qrs1,qrs2: out std_logic );
end dff1;

architecture async_set_reset of dff1 is
attribute syn_preserve : boolean;
attribute syn_preserve of qrs2 : signal is true;

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