Thread: VHDL oddity
View Single Post
  #4 (permalink)  
Old 09-21-2006, 09:49 AM
alessandro basili
Guest
 
Posts: n/a
Default Re: VHDL oddity

what about this:

column_out <= column_out + '1';

adding the ieee.std_logic_arith.all package?

smithodude wrote:
> OK, compiling and simulating this on Modelsim 5.6a and the design seems
> to work - DATA_OUT toggles between the two values.
>
> I did however need to change the 'column_out+1' line because the code
> is trying to add an integer to a std_Logic_vector
>
> column_out <=
> std_logic_vector(to_unsigned((to_integer(unsigned( column_out)) +
> 1),10));
>
>
> This is a long winded way of adding 1 to a std_logic_vector and I'm
> sure someone else may have a better more concise way.
>
> Hope this works
> Matt
>

Reply With Quote