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Old 04-14-2005, 03:56 AM
Jim Lewis
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Default Re: VHDL language of choice?

Ralf Hildebrandt wrote:

> Tim Hubberstey wrote:
>
>
>> Foremost among these, IMO, is the issue of a built-in pre-processor.
>> Nearly every person I have encountered who is just learning VHDL, but
>> has experience with another language, asks: Why is there no
>> pre-processor/macro capability?
>>
>> From the very beginning (VHDL'87), it has been stated that the
>> designers don't want a pre-processor ...

>
>
> Do we need a preprocessor, if something like the generate statements
> would be extended to the signal declaration and to the entity? Such a
> solution would offer configuration using one idea - not two like the
> parameter and defines in Verilog.
>
>
> Ralf


On a similar note, is there another answer for paramterizing
entity interfaces such as introducing some type of interface
abstraction.

---

BTW, the way I currently handle entities is to define all of
the signals. For designs that don't need some of the IO, I
tie off the inputs to constants and leave outputs open.
For FPGA tools this seems to be enough.

For ASIC tools, I instantiate the block inside of another block
with the only the IO I need and then during synthesis, remove
the level of hierarchy for the re-usable component. The result
is a single component without any unused IO. A few more tool
steps but it gets the job done.

Cheers,
Jim
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